US5374940A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for operating a plurality of graphics displays from a single computer
Assignee: University of Rochester
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Filing: 1991-06-04
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Granted: 1994-12-20
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Expires: 2011-06-04
Abstract
Abstract Multiple video boards of the general purpose type (e.g. EGA or VGA boards) and their associated monitors are operated by a single computer of the personal computer type, without modification of the computer hardware and while the video boards reside in their usual expansion slots which are provided by connectors on the mother board of the personal computer by a system which utilizes a flexible printed circuit board containing circuits which allows the processor (CPU) of the computer to present address and data signals which operate circuitry on the flexible boards to selectively enable or inhibit the communication of control signals (on the I/O and memory read and write control lines) to the video boards thereby enabling them to generate graphical images for their associated monitors. The signals on the address control and data lines are tapped and relayed either directly or after processing to the associated video board thereby enabling multiple video boards of the same or different types to be used concurrently by appropriate programming of the computer without the need to interchange hardware to switch between displays thereby reducing the inconvenience and potential hardware damage necessarily incident to such a hardware interchange procedure.
Inventors
- 👤 Mark A. Corio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:09
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14; G06F3/1423; G06F3/1438; H; H05; H05K; H05K1/00; H05K1/18; H05K1/189
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
336 words
A system for operating simultaneously a plurality of graphics displays in response to a plurality of digital data and control signals generated by a single central processing unit, which signals are presented at a plurality of outputs along a bus which is connected to said central processing unit, a plurality of separate graphics adaptor circuits connected to a corresponding graphics display for generating graphic image representing data in response to said data signals and said control signals and said plurality of displays presenting graphics images thereon, said system comprising a plurality of separate intercepting means each connected between a different one of said plurality of outputs and a different one of said plurality of adaptor circuits, and each of said intercepting means corresponding to a different one of said plurality of adaptor circuits, said intercepting means being operative for intercepting said control and data signals without interfering with the transmission of said data signals and those of said control signals used by said adaptor circuits for generating said image representing data, and means included in each of said plurality of intercepting means and responsive to said control and data signals for selectively blocking and applying control signals other than those which are used to generate said image representing data to said adaptor circuits to generate said image representing data therein with up-dated and un-updated data concurrently on each of said plurality of displays, and wherein said control signals include address signals and signals for controlling reading from and writing of data to said adaptor circuits, and said blocking and applying means of each of said intercepting means comprises (a) logic means for applying said control signals to said corresponding adaptor circuits when enabled, (b) decoding means responsive to said address signals for enabling selection of said corresponding adaptor circuits and the one of said plurality of graphics displays operated thereby and (c) selective enabling means enabled by said decoding means for selectively enabling said logic means in response to at least one of said data signals.
Claim 2
Independent Claim
336 words
A system for operating simultaneously a plurality of graphics displays in response to a plurality of digital data and control signals generated by a single central processing unit, which signals are presented at a plurality of outputs along a bus which is connected to said central processing unit, a plurality of separate graphics adaptor circuits connected to a corresponding graphics display for generating graphic image representing data in response to said data signals and said control signals and said plurality of displays presenting graphics images thereon, said system comprising a plurality of separate intercepting means each connected between a different one of said plurality of outputs and a different one of said plurality of adaptor circuits, and each of said intercepting means corresponding to a different one of said plurality of adaptor circuits, said intercepting means being operative for intercepting said control and data signals without interfering with the transmission of said data signals and those of said control signals used by said adaptor circuits for generating said image representing data, and means included in each of said plurality of intercepting means and responsive to said control and data signals for selectively blocking and applying control signals other than those which are used to generate said image representing data to said adaptor circuits to generate said image representing data therein with up-dated and un-updated data concurrently on each of said plurality of displays, and wherein said control signals include address signals and signals for controlling reading from and writing of data to said adaptor circuits, and said blocking and applying means of each of said intercepting means comprises (a) logic means for applying said control signals to said corresponding adaptor circuits when enabled, (b) decoding means responsive to said address signals for enabling selection of said corresponding adaptor circuits and the one of said plurality of graphics displays operated thereby and (c) selective enabling means enabled by said decoding means for selectively enabling said logic means in response to at least one of said data signals.
Claim 3
Dependent Claim
42 words
The system according to claim 1 wherein said decoding means includes means for programming said decoding means to provide a first output in response to a unique combination of said address signals, said selective enabling means being responsive to said first output.
Claim 4
Dependent Claim
75 words
The system according to claim 2 where said enabling means comprises register means enabled by said first output for storing said certain data signal to provide a second output corresponding thereto, and said logic means includes means responsive to said second output for selectively enabling said logic means to transfer said certain control signals to the one of said plurality of adaptor circuits corresponding to the intercepting means of which said logic means is comprised.
Claim 5
Dependent Claim
56 words
The system according to claim 3 wherein said logic means for said plurality of intercepting means includes a plurality of gates each selectively enabled by said second output for transferring a different one out of said certain control signals to said adaptor circuit corresponding to the one of said intercepting means of which it is comprised.
Claim 6
Dependent Claim
36 words
The system according to claim 4 further comprising means for initially conditioning said register means of one of said intercepting means to provide said second output of a value to enable the logic means responsive thereto.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-19 | 1998-06-20 | 1998-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-19 | 2002-06-20 | 2002-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-19 | 2006-06-20 | 2006-12-20 | $7700.00 | Window Closed / Lapsed |