US5375085A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Three-dimensional ferroelectric integrated circuit without insulation layer between memory layers
Assignee: Texas Instruments Inc
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Filing: 1992-09-30
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Granted: 1994-12-20
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Expires: 2012-09-30
Abstract
Abstract A ferroelectric integrated circuit is provided in which a first layer of conducting lines (14) is formed over an insulating base layer (10). A first ferroelectric layer (16) is formed overlying the first layer of conducting lines (14). A second layer of conducting lines (18) is formed overlying the first ferroelectric layer (16) with each of the conducting lines of the second layer of conducting lines (18) being substantially perpendicular to the conducting lines of the first layer of conducting lines (14). Potentials placed on selected conducting lines in the first and second layers of conducting lines (14 and 18) polarize areas of the first ferroelectric layer (16) between intersections of the selected conducting lines. Multiple layers may be stacked to form a three-dimensional ferroelectric integrated circuit.
Inventors
- 👤 Bruce E. Gnade
- 👤 Russell F. Pinizzotto
- 👤 Christopher L. Littler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:53
CPC Classifications
H; H10; H10B; H10B53/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
135 words
A ferroelectric integrated circuit, comprising: a base layer; a plurality of layers of first conducting lines overlying and substantially parallel to said base layer; a plurality of layers of second conducting lines, said second conducting lines being substantially perpendicular to said first conducting lines, each of said layers of second conducting lines being interleaved between successive layers of first conducting lines; and a plurality of ferroelectric layers directly interleaved between each layer of first conducting lines and each layer of second conducting lines, wherein each of said ferroelectric layers is in direct contact with adjacent ones of said ferroelectric layers; such that potentials placed on conducting lines in said layers of first and second conducting lines are capable of polarizing areas in said ferroelectric layers between intersecting conducting lines on which potentials have been placed.
Claim 2
Dependent Claim
135 words
A ferroelectric integrated circuit, comprising: a base layer; a plurality of layers of first conducting lines overlying and substantially parallel to said base layer; a plurality of layers of second conducting lines, said second conducting lines being substantially perpendicular to said first conducting lines, each of said layers of second conducting lines being interleaved between successive layers of first conducting lines; and a plurality of ferroelectric layers directly interleaved between each layer of first conducting lines and each layer of second conducting lines, wherein each of said ferroelectric layers is in direct contact with adjacent ones of said ferroelectric layers; such that potentials placed on conducting lines in said layers of first and second conducting lines are capable of polarizing areas in said ferroelectric layers between intersecting conducting lines on which potentials have been placed.
Claim 3
Dependent Claim
34 words
The integrated circuit of claim 1, wherein said areas capable of being polarized interact, such that polarization of a particular area is capable of causing polarization of other areas proximate to said particular area.
Claim 4
Dependent Claim
46 words
The integrated circuit of claim 1, and further comprising read and write circuitry coupled to said ferroelectric integrated circuit for storing and retrieving data from each of said areas of said ferroelectric layers between intersecting conducting lines in said layers of first and second conducting lines.
Claim 5
Dependent Claim
62 words
The integrated circuit of claim 3, wherein said read and write circuitry is operable to retrieve data by sensing capacitances in said areas of said ferroelectric layers between said intersecting conducting lines, and said read and write circuitry is operable to store data by polarizing said areas of said ferroelectric layers between said intersecting conducting lines on which potentials have been placed.
Claim 6
Dependent Claim
18 words
The integrated circuit of claim 3, wherein said read and write circuitry is formed in said integrated circuit.
Claim 7
Dependent Claim
27 words
The integrated circuit of claim 1, and further comprising a dielectric layer disposed overlying said base layer and underlying said plurality of layers of first conducting lines.
Claim 8
Dependent Claim
21 words
The integrated circuit of claim 1 wherein there are an even number of said layers of first and second conducting lines.
Claim 9
Dependent Claim
21 words
The integrated circuit of claim 1 wherein there are an odd number of said layers of first and second conducting lines.
Claim 10
Dependent Claim
16 words
The integrated circuit of claim 1 wherein there are an even number of said ferroelectric layers.
Claim 11
Dependent Claim
16 words
The integrated circuit of claim 1 wherein there are an odd number of said ferroelectric layers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-19 | 1998-06-20 | 1998-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-19 | 2002-06-20 | 2002-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-19 | 2006-06-20 | 2006-12-20 | $7700.00 | Window Closed / Lapsed |