US5375094A
Expired / Lapsed
US
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Nonvolatile semiconductor memory system with a plurality of erase blocks
Assignee: Toshiba Corp
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Filing: 1993-06-17
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Granted: 1994-12-20
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Expires: 2013-06-17
Abstract
Abstract A nonvolatile semiconductor memory system including a memory cell array (1) having a plurality of floating gate memory cell transistors (MC) arranged in a matrix of rows and columns with plurality of bit lines (BL) connected to the drains of the floating gate memory cell transistors arranged in a same column and a plurality of word lines (WL) connected to the control gates of the floating gate memory cell transistors in a same row, and a refresh circuit for periodically refreshing the stored data in the floating gate memory cell transistor.
Inventors
- 👤 Kiyomi Naruke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:59
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/08; G11C16/26; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
192 words
A nonvolatile semiconductor memory system comprising: a memory cell array having a plurality of floating gate memory cell transistors arranged in a matrix of rows and columns with a plurality of bit lines connected to the drains of said floating gate memory cell transistors arranged in a same column and a plurality of word lines connected to the control gates of said floating gate memory cell transistors arranged in a same row, wherein said memory cell transistors are divided into plural erase blocks comprising plural of said memory cell transistors and plural refresh blocks comprising plural of said memory cell transistors and wherein the memory cell transistors of a respective erase block are addressed for erasing stored data and the memory cell transistors of a respective refresh block are independently addressed for refreshing of stored data; and a control means for controlling sequentially performing erasing and refreshing operations in which data stored in the floating gate memory cell transistors of a respective erase block are erased in said erasing operation and the data stored in the floating gate memory cell transistors of a respective refresh block are refreshed in said refreshing operation.
Claim 2
Dependent Claim
192 words
A nonvolatile semiconductor memory system comprising: a memory cell array having a plurality of floating gate memory cell transistors arranged in a matrix of rows and columns with a plurality of bit lines connected to the drains of said floating gate memory cell transistors arranged in a same column and a plurality of word lines connected to the control gates of said floating gate memory cell transistors arranged in a same row, wherein said memory cell transistors are divided into plural erase blocks comprising plural of said memory cell transistors and plural refresh blocks comprising plural of said memory cell transistors and wherein the memory cell transistors of a respective erase block are addressed for erasing stored data and the memory cell transistors of a respective refresh block are independently addressed for refreshing of stored data; and a control means for controlling sequentially performing erasing and refreshing operations in which data stored in the floating gate memory cell transistors of a respective erase block are erased in said erasing operation and the data stored in the floating gate memory cell transistors of a respective refresh block are refreshed in said refreshing operation.
Claim 3
Dependent Claim
78 words
A nonvolatile semiconductor memory system according to claim 1, wherein said control means comprises: register means connected to said bit lines for temporarily storing the data read from the memory cell transistors; and refresh control means for controlling a refresh operation including the steps of reading data from said floating gate memory cell transistors, storing said data in said register means, and over-programming said data to said floating gate memory cell transistors from which said data were read.
Claim 4
Dependent Claim
38 words
A nonvolatile semiconductor memory system according to claim 2, wherein said refresh control means further comprises address counter means for storing an address which designates the memory cell transistor to which the refresh operation is to be conducted.
Claim 5
Dependent Claim
31 words
A nonvolatile semiconductor memory system according to claim 3, wherein said refresh control means further comprises a nonvolatile address register means for storing back-up address data for said address counter means.
Claim 6
Dependent Claim
74 words
A nonvolatile semiconductor memory system according to claim 4, wherein said refresh control means comprises means for producing a first control signal to store the contents of said address counter means as address data to said nonvolatile address register means before a power down and a second control signal to transfer said address data stored in said nonvolatile address register means to said address counter means when power is restored after said power down.
Claim 7
Dependent Claim
53 words
A nonvolatile semiconductor memory system according to claim 4, wherein after said refresh operation and in the event of a power-loss and a subsequent power restoration, said refresh control means comprises means for producing control signals to transfer the address data stored in said nonvolatile address register means to said address counter means.
Claim 8
Dependent Claim
23 words
A nonvolatile semiconductor memory system according to claim 3, wherein each refresh block corresponds to a respective address of said address counter means.
Claim 9
Dependent Claim
30 words
A nonvolatile semiconductor memory system according to claim 7, wherein said refresh control means further comprising nonvolatile address register means for storing back-up address data for said address counter means.
Claim 10
Dependent Claim
74 words
A nonvolatile semiconductor memory system according to claim 7, wherein said refresh control means comprises means for producing a first control signal to store the contents of said address counter means as address data to said non-volatile address register means before a power down and a second control signal to transfer said address data stored in said nonvolatile address register means to said address counter means when power is restored after said power down.
Claim 11
Dependent Claim
53 words
A nonvolatile semiconductor memory system according to claim 7, wherein after said refresh operation and in the event of a power-loss and a subsequent power restoration, said refresh control means comprises means for producing control signals to transfer the address data stored in said nonvolatile address register means to said address counter means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-19 | 1998-06-20 | 1998-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-19 | 2002-06-20 | 2002-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-19 | 2006-06-20 | 2006-12-20 | $7700.00 | Window Closed / Lapsed |