US5378925A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Routing method and arrangement for power lines and signal lines in a microelectronic device
Assignee: Seiko Epson Corp
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Filing: 1991-07-19
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Granted: 1995-01-03
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Expires: 2011-07-19
Abstract
Abstract In a semiconductor integrated circuit device such as a memory chip, the number of wirings is increasing as the memory capacity and the like increase. In improving the reliability and obtaining high access speed of a common bus in which these wirings are arranged, wirings in a second layer and via holes at jumpers used for interference portions of signal wirings and power supply wirings in a congested region of a common bus have become an issue. Accordingly, in the present invention, it is made possible to form wirings in the second layer having wide width and a plurality of via holes per one connecting point, thus realizing a semiconductor integrated circuit which has high reliability and high access speed by arranging a mother power supply wiring branched to the common bus line along the vicinity of processing circuits of signal wirings arranged in the common bus.
Inventors
- 👤 Minoru Sasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:17
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10D84/00; H10D89/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
285 words
An integrated circuit (IC) comprising: a) a plurality of memory blocks, formed in interior portions of said IC, each said memory block comprising a plurality of memory cells; b) a plurality of signal processing circuits, coupled by a corresponding plurality of conductive pathways to said memory blocks, formed in peripheral regions of said IC, said signal processing circuits having an area allocated for jumper formation; c) a first routing channel formed between said memory blocks and said signal processing circuits; d) a plurality of power supply buses oriented parallel to said first routing channel, and formed in a first conductive layer; and e) at least one second routing channel formed between at least one pair of memory blocks, said second routing channel orthogonal to said first routing channel; wherein at least two of said power supply buses are formed super adjacent said signal processing circuits, and wherein said conductive pathways comprise a first conductive segment formed in said first conductive layer, a second conductive segment, coupled to said first conductive segment by a contact structure, formed in a second conductive layer, said first conductive layer having a first sheet resistance and said second conductive layer having a second sheet resistance, said second sheet resistance being greater than or equal to said first sheet resistance, and said first conductive segment is orthogonal to said power supply buses, said second conductive segment is orthogonal to and disposed under at least two of said power supply buses, and said first conductive segment has at least a first portion, disposed in said first routing channel, that is parallel to said power buses, and a second portion, disposed in said second routing channel, that is orthogonal to said power buses.
Claim 2
Dependent Claim
285 words
An integrated circuit (IC) comprising: a) a plurality of memory blocks, formed in interior portions of said IC, each said memory block comprising a plurality of memory cells; b) a plurality of signal processing circuits, coupled by a corresponding plurality of conductive pathways to said memory blocks, formed in peripheral regions of said IC, said signal processing circuits having an area allocated for jumper formation; c) a first routing channel formed between said memory blocks and said signal processing circuits; d) a plurality of power supply buses oriented parallel to said first routing channel, and formed in a first conductive layer; and e) at least one second routing channel formed between at least one pair of memory blocks, said second routing channel orthogonal to said first routing channel; wherein at least two of said power supply buses are formed super adjacent said signal processing circuits, and wherein said conductive pathways comprise a first conductive segment formed in said first conductive layer, a second conductive segment, coupled to said first conductive segment by a contact structure, formed in a second conductive layer, said first conductive layer having a first sheet resistance and said second conductive layer having a second sheet resistance, said second sheet resistance being greater than or equal to said first sheet resistance, and said first conductive segment is orthogonal to said power supply buses, said second conductive segment is orthogonal to and disposed under at least two of said power supply buses, and said first conductive segment has at least a first portion, disposed in said first routing channel, that is parallel to said power buses, and a second portion, disposed in said second routing channel, that is orthogonal to said power buses.
Claim 3
Dependent Claim
13 words
The integrated circuit of claim 1 wherein said first conductive layer comprises aluminum.
Claim 4
Dependent Claim
23 words
The integrated circuit of claim 1 wherein said second conductive layer comprises a material selected from the group consisting of aluminum and polysilicon.
Claim 5
Dependent Claim
22 words
The integrated circuit of claim 1 further comprising at least one row decoder coupled to at least one of said memory blocks.
Claim 6
Dependent Claim
21 words
The integrated circuit of claim 1 further comprising a main power supply wiring that is orthogonal to said power supply buses.
Claim 7
Dependent Claim
361 words
An integrated circuit (IC) comprising: a) a plurality of memory blocks, formed in interior portions of said IC, each said memory block comprising a plurality of memory cells; b) a plurality of signal processing circuits, coupled by a corresponding plurality of conductive pathways to said memory blocks, formed in peripheral regions of said IC, said signal processing circuits having an area allocated for jumper formation; c) a first routing channel formed between said memory blocks and said signal processing circuits; d) a plurality of power supply buses, first portions of said plurality of power supply buses are oriented parallel to said first routing channel and formed in a first conductive layer; and e) at least one second routing channel formed between at least one pair of memory blocks, said second routing channel orthogonal to said first routing channel; wherein second portions of at least two of said power supply buses are arranged in said second routing channel and at least one of said conductive pathways is arranged between said second portions of said at least two power supply buses, and wherein said conductive pathways comprise a first conductive segment formed in said first conductive layer, a second conductive segment, coupled to said first conductive segment by a contact structure, formed in a second conductive layer, said first conductive layer having a first sheet resistance and said second conductive layer having a second sheet resistance, said second sheet resistance being greater than or equal to said first sheet resistance, and said first conductive segment is orthogonal to said first portions of said power supply buses, said second conductive segment is orthogonal to said first portions of said power supply buses, and said first conductive segment has at least a first portion, disposed in said first routing channel, that is parallel to said first portions of said power buses, and a second portion, disposed in said second routing channel, that is orthogonal to said first portions of said power buses, and wherein said at least two of said power supply buses are coupled to one another and cross said at least one pathway only in an area disposed over said second conductive segment.
Claim 8
Dependent Claim
361 words
An integrated circuit (IC) comprising: a) a plurality of memory blocks, formed in interior portions of said IC, each said memory block comprising a plurality of memory cells; b) a plurality of signal processing circuits, coupled by a corresponding plurality of conductive pathways to said memory blocks, formed in peripheral regions of said IC, said signal processing circuits having an area allocated for jumper formation; c) a first routing channel formed between said memory blocks and said signal processing circuits; d) a plurality of power supply buses, first portions of said plurality of power supply buses are oriented parallel to said first routing channel and formed in a first conductive layer; and e) at least one second routing channel formed between at least one pair of memory blocks, said second routing channel orthogonal to said first routing channel; wherein second portions of at least two of said power supply buses are arranged in said second routing channel and at least one of said conductive pathways is arranged between said second portions of said at least two power supply buses, and wherein said conductive pathways comprise a first conductive segment formed in said first conductive layer, a second conductive segment, coupled to said first conductive segment by a contact structure, formed in a second conductive layer, said first conductive layer having a first sheet resistance and said second conductive layer having a second sheet resistance, said second sheet resistance being greater than or equal to said first sheet resistance, and said first conductive segment is orthogonal to said first portions of said power supply buses, said second conductive segment is orthogonal to said first portions of said power supply buses, and said first conductive segment has at least a first portion, disposed in said first routing channel, that is parallel to said first portions of said power buses, and a second portion, disposed in said second routing channel, that is orthogonal to said first portions of said power buses, and wherein said at least two of said power supply buses are coupled to one another and cross said at least one pathway only in an area disposed over said second conductive segment.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-02 | 1998-07-04 | 1999-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-02 | 2002-07-04 | 2003-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-02 | 2006-07-04 | 2007-01-03 | $7700.00 | Window Closed / Lapsed |