US5379414A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Systems and methods for FDC error detection and prevention
Assignee: Sony Corp
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Filing: 1992-07-10
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Granted: 1995-01-03
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Expires: 2012-07-10
Abstract
Abstract A system and method which provides a complete software implementation of a device driver that is capable of detecting an undetectable data corruption problem without hardware redesign and/or internal modification to an existing FDC. The approach taken consists of software DMA shadowing and use of a software decoding network which allows the implementation of the invention to require a small amount of memory and only degrade the performance of the computer system a minimal amount when floppy diskette write operations occur.
Inventors
- 👤 Phillip M. Adams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:29
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/16; G06F11/1608; G06F11/1612; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1816; G11B27/00; G11B27/36; G06F11/30; G06F11/34; G06F11/3466; G06F11/3485
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
216 words
A method for detecting and preventing floppy diskette controller data transfer errors in computer systems having: a central processing unit (CPU); a system interrupt timer; a floppy diskette, the floppy diskette having at least one sector for receiving multiple data bytes; a floppy diskette controller (FDC) for controlling the transfer of data to the floppy diskette; means associated with the FDC for providing a data request (DREQ) signal and a data acknowledge (DACK) signal, the DREQ signal being provided when data transfer is requested and the DACK signal being provided when data transfer is permitted; and means for counting data bytes transferred to the floppy diskette, said counting means providing a data transfer byte count, the method comprising the steps of: determining if a requested computer system operation is a floppy diskette write operation; reading the data transfer byte count provided by said counting means; monitoring data byte transfers to the floppy diskette so as to determine when a last data byte is being transferred to a sector of the floppy diskette; measuring time between the data request (DREQ) and data acknowledge (DACK) signals for said last data byte transfer to a sector of the floppy diskette; and forcing an error condition if the measured time between said DREQ and DACK signals exceeds a specified value.
Claim 2
Independent Claim
216 words
A method for detecting and preventing floppy diskette controller data transfer errors in computer systems having: a central processing unit (CPU); a system interrupt timer; a floppy diskette, the floppy diskette having at least one sector for receiving multiple data bytes; a floppy diskette controller (FDC) for controlling the transfer of data to the floppy diskette; means associated with the FDC for providing a data request (DREQ) signal and a data acknowledge (DACK) signal, the DREQ signal being provided when data transfer is requested and the DACK signal being provided when data transfer is permitted; and means for counting data bytes transferred to the floppy diskette, said counting means providing a data transfer byte count, the method comprising the steps of: determining if a requested computer system operation is a floppy diskette write operation; reading the data transfer byte count provided by said counting means; monitoring data byte transfers to the floppy diskette so as to determine when a last data byte is being transferred to a sector of the floppy diskette; measuring time between the data request (DREQ) and data acknowledge (DACK) signals for said last data byte transfer to a sector of the floppy diskette; and forcing an error condition if the measured time between said DREQ and DACK signals exceeds a specified value.
Claim 3
Independent Claim
258 words
A method for detecting and preventing floppy diskette controller data transfer errors in computer systems having: a central processing unit (CPU); a system interrupt timer; a floppy diskette, the floppy diskette having at least one sector for receiving multiple data bytes; a floppy diskette controller (FDC) for controlling the transfer of data to the floppy diskette; means associated with the FDC for providing a data request (DREQ) signal and a data acknowledge (DACK) signal, the DREQ signal being provided when data transfer is requested and the DACK signal being provided when data transfer is permitted; and means for counting data bytes transferred to the floppy diskette, said counting means providing a data transfer byte count, the method comprising the steps of: determining if a requested computer system operation is a floppy diskette write operation; hooking an interrupt vector and directing it to an interposer routine; reprogramming the system interrupt timer to interrupt faster than normal; installing and calling a software decoding network call vector; reading the data transfer byte count provided by said counting means; monitoring data byte transfers to the floppy diskette so as to determine when a last data byte is being transferred to a sector of the floppy diskette; measuring time between the data request (DREQ) and data acknowledge (DACK) signals for said last data byte transfer to a sector of the floppy diskette; forcing an error condition if the measured time between said DREQ and DACK signals exceeds a specified value; reprogramming the system interrupt timer to interrupt normally; and unhooking said interrupt vector.
Claim 4
Independent Claim
258 words
A method for detecting and preventing floppy diskette controller data transfer errors in computer systems having: a central processing unit (CPU); a system interrupt timer; a floppy diskette, the floppy diskette having at least one sector for receiving multiple data bytes; a floppy diskette controller (FDC) for controlling the transfer of data to the floppy diskette; means associated with the FDC for providing a data request (DREQ) signal and a data acknowledge (DACK) signal, the DREQ signal being provided when data transfer is requested and the DACK signal being provided when data transfer is permitted; and means for counting data bytes transferred to the floppy diskette, said counting means providing a data transfer byte count, the method comprising the steps of: determining if a requested computer system operation is a floppy diskette write operation; hooking an interrupt vector and directing it to an interposer routine; reprogramming the system interrupt timer to interrupt faster than normal; installing and calling a software decoding network call vector; reading the data transfer byte count provided by said counting means; monitoring data byte transfers to the floppy diskette so as to determine when a last data byte is being transferred to a sector of the floppy diskette; measuring time between the data request (DREQ) and data acknowledge (DACK) signals for said last data byte transfer to a sector of the floppy diskette; forcing an error condition if the measured time between said DREQ and DACK signals exceeds a specified value; reprogramming the system interrupt timer to interrupt normally; and unhooking said interrupt vector.
Claim 5
Dependent Claim
51 words
A method for detecting and preventing floppy diskette controller data transfer errors as defined in claim 1 wherein said means for counting data bytes comprises a data transfer count register of a direct memory access (DMA) controller and wherein the reading step comprises reading the DMA controller's data transfer count register.
Claim 6
Dependent Claim
33 words
A method for detecting and preventing floppy diskette controller data transfer errors as defined in claim 1 further comprising the step of hooking an interrupt vector and directing it to an interposer routine.
Claim 7
Dependent Claim
32 words
A method for detecting and preventing floppy diskette controller data transfer errors as defined in claim 1 further comprising the step of reprogramming the system interrupt timer to interrupt faster than normal.
Claim 8
Independent Claim
30 words
A method for detecting and preventing floppy diskette controller data transfer errors as defined in claim further comprising the step of installing and calling a software decoding network call vector.
Claim 9
Dependent Claim
51 words
A method for detecting and preventing floppy diskette controller data transfer errors as defined in claim 2 wherein said means for counting data bytes comprises a data transfer count register of a direct memory access (DMA) controller and wherein the reading step comprises reading the DMA controller's data transfer count register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-02 | 1998-07-04 | 1999-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-02 | 2002-07-04 | 2003-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-02 | 2006-07-04 | 2007-01-03 | $7700.00 | Window Closed / Lapsed |