Structure and method for flash eprom memory erasable by sectors

Claim 2

An integrated circuit, comprising: first and second sectors of nonvolatile memory cells, each said sector having a respective erase terminal which is connected to cause erasure of all cells in said respective sector when an erase voltage is applied thereto; a respective parallel selection transistor, and a respective individual selection transistor, both connected to said erase terminal of each said sector; each said erase terminal being operatively connected, through said respective individual selection transistor and a respective proper load resistor, to an erasing voltage terminal; each said erase terminal being operatively connected, through said respective parallel selection transistor and a parallel-erasing-load resistor, to said erasing voltage terminal; wherein each said sector is connected to a separate respective one of said parallel erasing resistors, but said parallel-erasing-load resistor is common to both said sectors.

Claim 3

The integrated circuit of claim 1, wherein each said cell is a floating-gate memory cell.

Claim 4

The integrated circuit of claim 1, wherein each said cell is an NMOS floating-gate memory cell, and all said cells in each respective sector have source terminals connected together and to said erase terminal of the sector.

Claim 5

The integrated circuit of claim 1, comprising multiple ones of said parallel-selection transistors, each connected to a separate respective plurality of said parallel selection transistors.

Claim 6

The integrated circuit of claim 1, further comprising routing logic which is connected to receive sector erasure signals, and accordingly: if the sector erasure signals indicate that all of said sectors are to be erased, then turning on said respective parallel selection transistors for that particular selected sector; and if the sector erasure signals indicate that only one of said sectors is to be erased, then turning on said respective individual selection transistor for that particular selected sector.

Claim 7

An integrated circuit, comprising: multiple sectors of nonvolatile memory cells, each said sector having a respective erase terminal which is connected to cause erasure of all cells in said respective sector when an erase voltage is applied thereto; a respective parallel selection transistor, and a respective individual selection transistor, both connected to said erase terminal of each said sector; each said sector having said erase terminal thereof operatively connected, through said respective individual selection transistor and a respective proper load resistor, to an erasing voltage terminal; each said erase terminal being operatively connected, through said respective parallel selection transistor and a common parallel-erasing-load resistor, to said erasing voltage terminal; wherein each said sector is connected to a separate respective one of said parallel erasing resistors, but said parallel-erasing-load resistor is common to all of said sectors.

Claim 8

An integrated circuit, comprising: multiple sectors of nonvolatile memory cells, each said sector having a respective erase terminal which is connected to cause erasure of all cells in said respective sector when an erase voltage is applied thereto; a respective parallel selection transistor, and a respective individual selection transistor, both connected to said erase terminal of each said sector; each said sector having said erase terminal thereof operatively connected, through said respective individual selection transistor and a respective proper load resistor, to an erasing voltage terminal; each said erase terminal being operatively connected, through said respective parallel selection transistor and a common parallel-erasing-load resistor, to said erasing voltage terminal; wherein each said sector is connected to a separate respective one of said parallel erasing resistors, but said parallel-erasing-load resistor is common to all of said sectors.

Claim 9

The integrated circuit of claim 6, wherein each said cell is a floating-gate memory cell.

Claim 10

The integrated circuit of claim 6, wherein each said cell is an NMOS floating-gate memory cell, and all said cells in each respective sector have source terminals connected together and to said erase terminal of the sector.

Claim 11

The integrated circuit of claim 6, comprising multiple ones of said parallel-selection transistors, each connected to a separate respective plurality of said parallel selection transistors.

Claim 12

The integrated circuit of claim 6, further comprising routing logic which is connected to receive sector erasure signals, and accordingly: if the sector erasure signals indicate that all of said sectors are to be erased, then turning on said respective parallel selection transistors for that particular selected sector; and if the sector erasure signals indicate that only one of said sectors is to be erased, then turning on said respective individual selection transistor for that particular selected sector.

Claim 15

A device for the erasure of sectors of a memory map of a flash EPROM according to claim 11, wherein the routing means enable the assigning of a resistive element proper to each sector when the sectors are selected individually to be erased.

Claim 16

A device for the erasure of sectors of a memory map according to claim 11, comprising selection means that include, for each of the sectors, a first transistor in series with the predetermined resistive element, placed between the source of the sector and the source of the erasing voltage, and a second transistor in series with the resistive element proper to the sector, placed between the source of the sector and a source of erasing voltage.

Claim 17

A device for the erasure of a memory map of a flash EPROM according to claim 13, wherein the routing means include means to respectively turn on and turn off the first transistor and the second transistor of the sectors selected simultaneously to be erased, so that the erasure voltage is applied by the predetermined resistive element and to respectively turn off and turn on the first transistor and the second transistor of a sector selected individually to be erased, so that the erasing voltage is applied by the resistive element proper to the sector.

Claim 18

A device for the erasure of a memory map of a flash EPROM according to claim 14, wherein the routing means include logic gates.

Claim 19

A flash EPROM memory, having a memory map divided into sectors having sources comprising resistive elements to apply an erasing voltage to said sources of sectors selected to be erased, wherein said memory comprises routing means enabling the assigning of a predetermined resistive element to several sectors selected simultaneously to be erased, so as to apply the erasing voltage to said resistive element.

Claim 20

A flash EPROM memory, having a memory map divided into sectors having sources comprising resistive elements to apply an erasing voltage to said sources of sectors selected to be erased, wherein said memory comprises routing means enabling the assigning of a predetermined resistive element to several sectors selected simultaneously to be erased, so as to apply the erasing voltage to said resistive element.

Claim 21

A flash EPROM memory having a memory map divided into sectors according to claim 16, wherein the routing means enable the assigning of a resistive element proper to each sector selected individually to be erased, so as to apply the erasing voltage to the resistive element proper to this sector.