Method of forming a self-aligned low density drain inverted thin film transistor

Claim 2

A process for forming a semiconductor device having an inverted thin film transistor, comprising the following steps: a) forming a first dielectric layer over a semiconductor substrate; b) forming a thin film transistor gate over said first dielectric layer; c) forming a second dielectric layer over said transistor gate; d) forming a semiconductor layer over said second dielectric layer and over said thin film gate; e) forming an implant masking layer over said semiconductor layer; f) forming an etch mask layer over said transistor gate and over a portion of said implant masking layer, thereby covering portions of said implant masking layer and leaving portions of said implant masking layer exposed; g) removing said exposed portions of said implant masking layer thereby forming exposed portions of said semiconductor layer; h) doping said exposed portions of said semiconductor layer; i) undercutting said etch mask to remove a portion of said implant masking layer from under said etch mask and further exposing said semiconductor layer; and j) subsequent to step i), doping said semiconductor layer exposed during step i), wherein said doping steps form thin film transistor source and drain regions, and said source and drain regions and said gate form portions of an inverted thin film transistor device.

Claim 3

The process of claim 1 wherein steps g) and i) are performed during a single etch step.

Claim 4

The process of claim 1 further comprising the step of performing a voltage adjust implant on said semiconductor layer by doping said semiconductor layer.

Claim 5

The process of claim 3 wherein said voltage adjust implant dopes said semiconductor layer with an N-type dopant at a dose of 4.6E12 ions/cm 2 , said step h) dopes said semiconductor layer with a P-type dopant at a dose of 5.0E14 ions/cm 2 , and said step j) dopes said semiconductor layer with a P-type dopant at a dose of 5.0E12 ions/cm 2 .

Claim 6

The process of claim 1, further comprising the step of removing said etch mask between steps i) and j).

Claim 7

The process of claim 5, further comprising the step of removing said implant masking layer after step j).

Claim 8

The process of claim 6, wherein said implant masking layer comprises plasma oxide having a thickness of 2000 Å.

Claim 9

The process of claim 1 wherein said step i) comprises the use of hydrofluoric acid as an etchant to undercut said etch mask.

Claim 10

The process of claim 1 wherein said step i) comprises the use of a plasma as an etchant to undercut said etch mask.

Claim 11

A process for forming an inverted lightly doped drain thin film transistor for a static random access memory device, comprising the following steps: a) forming a first dielectric layer over a semiconductor substrate; b) forming a thin film transistor gate over said first dielectric layer; c) forming a second dielectric layer over said transistor gate; d) forming a semiconductor layer over said second dielectric layer and over said thin film gate; e) forming an implant masking layer over said semiconductor layer; f) forming an etch mask layer over said transistor gate and over a portion of said implant masking layer, thereby covering portions of said implant masking layer and leaving portions of said implant masking layer exposed; g) removing said exposed portions of said implant masking layer thereby forming exposed portions of said semiconductor layer; h) doping said exposed portions of said semiconductor layer; i) undercutting said etch mask to remove a portion of said implant masking layer from under said etch mask and further exposing said semiconductor layer; and j) subsequent to step i), doping said semiconductor layer exposed during step i); wherein said doping steps form thin film transistor source and drain regions, and said source and drain regions and said gate form portions of an inverted thin film transistor device.

Claim 12

A process for forming an inverted lightly doped drain thin film transistor for a static random access memory device, comprising the following steps: a) forming a first dielectric layer over a semiconductor substrate; b) forming a thin film transistor gate over said first dielectric layer; c) forming a second dielectric layer over said transistor gate; d) forming a semiconductor layer over said second dielectric layer and over said thin film gate; e) forming an implant masking layer over said semiconductor layer; f) forming an etch mask layer over said transistor gate and over a portion of said implant masking layer, thereby covering portions of said implant masking layer and leaving portions of said implant masking layer exposed; g) removing said exposed portions of said implant masking layer thereby forming exposed portions of said semiconductor layer; h) doping said exposed portions of said semiconductor layer; i) undercutting said etch mask to remove a portion of said implant masking layer from under said etch mask and further exposing said semiconductor layer; and j) subsequent to step i), doping said semiconductor layer exposed during step i); wherein said doping steps form thin film transistor source and drain regions, and said source and drain regions and said gate form portions of an inverted thin film transistor device.

Claim 13

The process of claim 10 wherein steps g) and i) are performed during a single etch step.

Claim 14

The process of claim 10 further comprising the step of performing a voltage adjust implant on said semiconductor layer by doping said semiconductor layer.

Claim 15

The process of claim 12 wherein said voltage adjust implant dopes said semiconductor layer with an N-type dopant at a dose of ions/cm 2 , said step h) dopes said semiconductor layer with a P-type dopant at a dose of 5.0E14 ions/cm 2 , and said step j) dopes said semiconductor layer with a P-type dopant at a dose of 5.0E12 ions/cm 2 .

Claim 16

The process of claim 10, further comprising the step of removing said etch mask between steps i) and j).

Claim 17

The process of claim 14, further comprising the step of removing said implant masking layer after step j).

Claim 18

The process of claim 15, wherein said implant masking layer comprises plasma oxide having a thickness of 2000 Å.

Claim 19

The process of claim 10 wherein said step i) comprises the use of hydrofluoric acid as an etchant to undercut said etch mask.

Claim 20

The process of claim 10 wherein said step i) comprises the use of a plasma as an etchant to undercut said etch mask.

Claim 21

A process for forming an inverted lightly doped drain thin film transistor for a static random access memory device, comprising the following steps: a) forming a first oxide layer over a semiconductor support layer; b) forming a transistor gate of doped polycrystalline silicon over said first oxide layer; c) forming a second oxide layer over said transistor gale; d) forming a polycrystalline silicon layer over said second oxide layer; e) forming a third oxide layer over said polycrystalline silicon layer, said third oxide layer having a thickness of at least 2000 Å; f) forming an etch mask layer over said transistor gate and over a portion of said third oxide layer, thereby covering portions of said third oxide layer and leaving portions of said third oxide layer exposed; g) removing said exposed portions of said third oxide layer thereby leaving portions of said polycrystalline silicon layer exposed; h) doping said exposed portions of said polycrystalline silicon layer with a P-type dopant at a dose of 5.0E14 ions/cm 2 ; i) undercutting said etch mask layer to remove portions of said third oxide layer, said undercutting further exposing said polycrystalline layer; j) removing said etch mask; and k) doping said polycrystalline silicon layer exposed during step i), with an N-type dopant at a dose of 5.0E12 ions/cm 2 ; thereby forming a transistor source, a transistor drain, and a transistor channel in said polycrystalline silicon layer.

Claim 22

A process for forming an inverted lightly doped drain thin film transistor for a static random access memory device, comprising the following steps: a) forming a first oxide layer over a semiconductor support layer; b) forming a transistor gate of doped polycrystalline silicon over said first oxide layer; c) forming a second oxide layer over said transistor gale; d) forming a polycrystalline silicon layer over said second oxide layer; e) forming a third oxide layer over said polycrystalline silicon layer, said third oxide layer having a thickness of at least 2000 Å; f) forming an etch mask layer over said transistor gate and over a portion of said third oxide layer, thereby covering portions of said third oxide layer and leaving portions of said third oxide layer exposed; g) removing said exposed portions of said third oxide layer thereby leaving portions of said polycrystalline silicon layer exposed; h) doping said exposed portions of said polycrystalline silicon layer with a P-type dopant at a dose of 5.0E14 ions/cm 2 ; i) undercutting said etch mask layer to remove portions of said third oxide layer, said undercutting further exposing said polycrystalline layer; j) removing said etch mask; and k) doping said polycrystalline silicon layer exposed during step i), with an N-type dopant at a dose of 5.0E12 ions/cm 2 ; thereby forming a transistor source, a transistor drain, and a transistor channel in said polycrystalline silicon layer.

Claim 23

The process of claim 19 wherein steps g) and i) are performed during a single etch step.

Claim 24

The process of claim 19 wherein step i) comprises the use of hydrofluoric acid as an etchant to undercut said etch mask.

Claim 25

The process of claim 19 wherein step i) comprises the use of a oxide-selective plasma as an etchant to undercut said etch mask.

Claim 26

The process of claim 19 further comprising the step of adjusting a threshold voltage of said polycrystalline silicon layer by doping said polycrystalline silicon layer with an P-type dopant at a dose of 4.6E12 ions/cm 2 .

Claim 27

The process of claim 1, further comprising the step removing said implant masking layer after step j).

Claim 28

The process of claim 10, further comprising the step of removing said implant making layer after step j).

Claim 29

The process of claim 19, further comprising the step of removing said third oxide layer after step k).