Symmetrical decoder

Claim 2

A symmetrical decoder for graphic processing, comprising: first input means for receiving initial coordinate signals representing coordinates of two points in a window, processing said initial coordinate signals, and outputting processed coordinate signals; second input means for receiving initial direction signals representing a direction between the two points in the window, processing said initial direction signals, and outputting processed direction signals; and operation means for determining a relationship between the two points utilizing a previously determined array of sets of coordinates and relationships corresponding to each of the sets of coordinates on the basis of the processed coordinate signals and processed direction signals supplied from said first and second input means, wherein said array is symmetrical around a centerpoint of said window, and wherein said first input means includes a plurality of multiplexers for multiplexing the received initial coordinate signals to provide processed coordinate signals.

Claim 3

A symmetrical decoder for graphic processing, comprising: first input means for receiving initial coordinate signals representing coordinates of two points in a window, processing said initial coordinate signals, and outputting processed coordinate signals; second input means for receiving initial direction signals representing a direction between the two points in the window, processing said initial direction signals, and outputting processed direction signals; and operation means for determining a relationship between the two points utilizing a previously determined array of sets of coordinates and relationships corresponding to each of the sets of coordinates on the basis of the processed coordinate signals and processed direction signals supplied from said first and second input means, wherein said array is symmetrical around a centerpoint of said window, and wherein said first input means includes an AND circuit and an exclusive OR circuit for electrically processing the received initial direction signals and for providing processed direction signals as control data signals for the first input means.

Claim 4

A symmetrical decoder for graphic processing, comprising: first input means for receiving initial coordinate signals representing coordinates of two points in a window, processing said initial coordinate signals, and outputting processed coordinate signals; second input means for receiving initial direction signals representing a direction between the two points in the window, processing said initial direction signals, and outputting processed direction signals; and operation means for determining a relationship between the two points utilizing a previously determined array of sets of coordinates and relationships corresponding to each of the sets of coordinates on the basis of the processed coordinate signals and processed direction signals supplied from said first and second input means, wherein said array is symmetrical around a centerpoint of said window, and wherein said first input means includes an AND circuit and an exclusive OR circuit for electrically processing the received initial direction signals and for providing processed direction signals as control data signals for the first input means.

Claim 5

The symmetrical decoder for graphic processing according to claim 1, wherein said second input means includes an AND circuit and an exclusive OR circuit for electrically processing the received initial direction signals, and wherein said plurality of multiplexers are controlled by output signals of said AND circuit and said exclusive OR circuit.

Claim 6

A symmetrical decoder for graphic processing, comprising: first input means for receiving initial coordinate signals representing coordinates of two points in a window, processing said initial coordinate signals, and outputting processed coordinate signals; second input means for receiving initial direction signals representing a direction between the two points in the window, processing said initial direction signals, and outputting processed direction signals; and operation means for determining a relationship between the two points utilizing a previously determined array of sets of coordinates and relationships corresponding to each of the sets of coordinates on the basis of the processed coordinate signals and processed direction signals supplied from said first and second input means, wherein said array is symmetrical around a centerpoint of said window, said operation means includes a decoding circuit for decoding the processed coordinate signals and providing a plurality of output signals as a decoded output and said operation means for logically determining a relationship between the two points further includes an OR circuit for performing a logical OR operation on the plurality of output signals of said decoding circuit.

Claim 7

A symmetrical decoder for graphic processing, comprising: first input means for receiving initial coordinate signals representing coordinates of two points in a window, processing said initial coordinate signals, and outputting processed coordinate signals; second input means for receiving initial direction signals representing a direction between the two points in the window, processing said initial direction signals, and outputting processed direction signals; and operation means for determining a relationship between the two points utilizing a previously determined array of sets of coordinates and relationships corresponding to each of the sets of coordinates on the basis of the processed coordinate signals and processed direction signals supplied from said first and second input means, wherein said array is symmetrical around a centerpoint of said window, said operation means includes a decoding circuit for decoding the processed coordinate signals and providing a plurality of output signals as a decoded output and said operation means for logically determining a relationship between the two points further includes an OR circuit for performing a logical OR operation on the plurality of output signals of said decoding circuit.