Semiconductor memory device including redundancy circuit

Claim 2

A semiconductor memory device, comprising: a plurality of memory cell array blocks, each including a plurality of selecting lines and a plurality of memory cells connected to said plurality of selecting lines; a plurality of first selecting means provided corresponding to said plurality of memory cell array blocks, for each selecting any of the plurality of selecting lines in a corresponding one of said memory cell array blocks; a plurality of redundant selecting lines provided corresponding to said plurality of memory cell array blocks; a plurality of redundant memory cells connected to said plurality of redundant selecting lines; a plurality of redundant circuit means each corresponding to one or a number of said plurality of redundant selecting lines, each of said plurality of redundant circuit means including setting means in which information as to whether or not the corresponding one or number of said plurality of redundant selecting lines being used is set in advance, program means in which an address of a selecting liner in any of said plurality of memory cell array blocks to be substituted by the corresponding one or number of said plurality of redundant selecting lines can be programmed, and second selecting means responsive to outputs of said setting means and said program means for selecting the corresponding one or number of said plurality of redundant selecting lines; and inactivating means responsive to outputs of said plurality of redundant circuit means for inactivating said plurality of first selecting means when one or a number said plurality of redundant selecting lines are selected by any of said plurality of redundant circuit means.

Claim 3

The semiconductor memory device according to claim 1, wherein each said second selecting means generates a redundant selecting line activating signal for selecting the corresponding one or number of said plurality of redundant selecting lines when use of one of said plurality of redundant selecting lines is set in said setting means and an address designated by an externally applied address signal matches with an address programmed into said program means.

Claim 4

The semiconductor memory device according to claim 2, wherein said inactivating means includes: logic gate means for generating an inactivating signal for inactivating said plurality of first selecting means when said redundant selecting line activating signal is generated from any of said plurality of redundant circuit means.

Claim 5

The semiconductor memory device according to claim 3, further comprising: block selecting means for selectively generating a plurality of block selecting signals for selecting said plurality of first selecting means, respectively, said block selecting means being rendered inactive in response to said inactivating signal from said inactivating means.

Claim 6

The semiconductor memory device according to claim 4, wherein said block selecting means includes: a plurality of block selectors corresponding to said plurality of memory cell array blocks, each of said plurality of block selectors generating a block selecting signal for bringing a corresponding one of said first selecting means into a selecting state in response to an externally applied block address signal.

Claim 7

The semiconductor memory device according to claim 5, further comprising: a plurality of sense amplifier means provided corresponding to said plurality of memory cell array blocks, for each amplifying data read from memory cells connected to a selected selecting line in a corresponding one of said memory cell array blocks or from memory cells connected to a corresponding redundant selecting line, wherein said block selecting means responds to said plurality of redundant selecting line activating signals and said inactivating signal to activate sense amplifier means corresponding to a selected memory cell array block or a selected redundant selecting line at the time of a reading operation.

Claim 8

The semiconductor memory device according to claim 6, further comprising: a plurality of writing means provided corresponding to said plurality of memory cell array blocks, for each writing data into memory cells connected to a selected selecting line in a corresponding memory cell array block or into memory cells connected to a corresponding redundant selecting line, wherein said block selecting means responds to said plurality of redundant selecting line activating signals and said inactivating signal to activate writing means corresponding to a selected memory cell array block or a selected redundant selecting line at the time of a writing operation.

Claim 9

The semiconductor memory device according to claim 3, wherein said plurality of first selecting means are rendered inactive in response to said inactivating signal from said inactivating means.

Claim 10

The semiconductor memory device according to claim 8, further comprising: block selecting means for generating a plurality of block selecting signals for selecting a plurality of memory cell array blocks, respectively; a plurality of sense amplifier means provided corresponding to said plurality of memory cell array blocks, for each amplifying data read from memory cells connected to a selected selecting line in a corresponding one of said memory cell array blocks or from memory cells connected to a corresponding one of said redundant selecting lines; and a plurality of activating means provided corresponding to said plurality of memory cell array blocks for each activating a corresponding one of said sense amplifier means, each of said plurality of activating-means activating or inactivating a corresponding one of said sense amplifier means in response to a corresponding one of said block selecting signals, a corresponding one of said redundant selecting line activating signals and said inactivating signal at the time of a reading operation.

Claim 11

The semiconductor memory device according to claim 9, further comprising: a plurality of writing means provided corresponding to said plurality of memory cell array blocks, for each writing externally applied data into a corresponding one of said memory cell array blocks or a corresponding redundant selecting line, wherein each of said plurality of activating means activates or inactivates a corresponding one of said sense amplifier means in response to a corresponding one of said block selecting signals, a corresponding one of said redundant selecting line activating signals and said inactivating signal at the time of a writing operation.

Claim 12

The semiconductor memory device according to claim 10, wherein each of said plurality of activating means includes: first transfer gate means for outputting as an activating signal a signal responsive to a redundant selecting line activating signal when said inactivating signal is rendered active, and second transfer gate means for outputting as an activating signal a signal responsive to a corresponding block selecting signal when said inactivating signal is rendered inactive.

Claim 13

A semiconductor memory device, comprising: a plurality of memory cell array blocks each including a plurality of selecting lines and a plurality of memory cells connected to said plurality of selecting lines; a plurality of first selecting means provided corresponding to said plurality of memory cell array blocks, for each selecting any of the plurality of selecting lines in a corresponding one of said memory cell array blocks; a plurality of redundant selecting lines provided corresponding to said plurality of memory cell array blocks; a plurality of redundant memory cells connected to said plurality of redundant selecting lines; a plurality of redundant circuit means each corresponding to a number of said plurality of redundant selecting lines, said plurality of redundant circuit means being smaller in number than said plurality of memory cell array blocks, each of said plurality of redundant circuit means including setting means in which information as to whether or not the corresponding number of said plurality of redundant selecting lines are used is set in advance, program means in which an address of a selecting line in any of said plurality of memory cell array blocks to be substituted by the corresponding number of said plurality of redundant selecting lines can be programmed, and second selecting means responsive to outputs of said setting means and said program means for selecting the corresponding number of said plurality of redundant selecting lines; inactivating means responsive to outputs of said plurality of redundant circuit means for inactivating said plurality of first selecting means when a number of said plurality of redundant selecting lines are selected by any of said plurality of redundant circuit means; and third selecting means for selecting one of said number of the plurality of redundant selecting lines selected by each said second selecting means.

Claim 14

A semiconductor memory device, comprising: a plurality of memory cell array blocks each including a plurality of selecting lines and a plurality of memory cells connected to said plurality of selecting lines; a plurality of first selecting means provided corresponding to said plurality of memory cell array blocks, for each selecting any of the plurality of selecting lines in a corresponding one of said memory cell array blocks; a plurality of redundant selecting lines provided corresponding to said plurality of memory cell array blocks; a plurality of redundant memory cells connected to said plurality of redundant selecting lines; a plurality of redundant circuit means each corresponding to a number of said plurality of redundant selecting lines, said plurality of redundant circuit means being smaller in number than said plurality of memory cell array blocks, each of said plurality of redundant circuit means including setting means in which information as to whether or not the corresponding number of said plurality of redundant selecting lines are used is set in advance, program means in which an address of a selecting line in any of said plurality of memory cell array blocks to be substituted by the corresponding number of said plurality of redundant selecting lines can be programmed, and second selecting means responsive to outputs of said setting means and said program means for selecting the corresponding number of said plurality of redundant selecting lines; inactivating means responsive to outputs of said plurality of redundant circuit means for inactivating said plurality of first selecting means when a number of said plurality of redundant selecting lines are selected by any of said plurality of redundant circuit means; and third selecting means for selecting one of said number of the plurality of redundant selecting lines selected by each said second selecting means.

Claim 17

A semiconductor memory device, comprising: a plurality of memory cell array blocks each including a plurality of selecting lines and a plurality of memory cells connected to said plurality of selecting lines; a plurality of first selecting means provided corresponding to said plurality of memory cell array blocks, for each selecting any of the plurality of selecting lines in a corresponding one of said memory cell array blocks; a plurality of redundant selecting lines provided corresponding to said plurality of memory cell array blocks; a plurality of redundant memory cells connected to said plurality of redundant selecting lines; a plurality of redundant circuit means each corresponding to a number of said plurality of redundant selecting lines, said plurality of redundant circuit means being smaller in number than said plurality of memory cell array blocks, each of said plurality of redundant circuit means including setting means in which information as to whether or not the corresponding number of said plurality of redundant selecting lines are used is set in advance, program means in which an address of a selecting line in any of said plurality of memory cell array blocks to be substituted by the corresponding number of said plurality of redundant selecting lines can be programmed, and second selecting means responsive to outputs of said setting means and said program means for selecting the corresponding number of said plurality of redundant selecting lines; and inactivating means responsive to outputs of said plurality of redundant circuit means for inactivating said plurality of first selecting means when a number of said plurality of redundant selecting lines are selected by any of said plurality of redundant circuit means.

Claim 18

A semiconductor memory device, comprising: a plurality of memory cell array blocks each including a plurality of selecting lines and a plurality of memory cells connected to said plurality of selecting lines; a plurality of first selecting means provided corresponding to said plurality of memory cell array blocks, for each selecting any of the plurality of selecting lines in a corresponding one of said memory cell array blocks; a plurality of redundant selecting lines provided corresponding to said plurality of memory cell array blocks; a plurality of redundant memory cells connected to said plurality of redundant selecting lines; a plurality of redundant circuit means each corresponding to a number of said plurality of redundant selecting lines, said plurality of redundant circuit means being smaller in number than said plurality of memory cell array blocks, each of said plurality of redundant circuit means including setting means in which information as to whether or not the corresponding number of said plurality of redundant selecting lines are used is set in advance, program means in which an address of a selecting line in any of said plurality of memory cell array blocks to be substituted by the corresponding number of said plurality of redundant selecting lines can be programmed, and second selecting means responsive to outputs of said setting means and said program means for selecting the corresponding number of said plurality of redundant selecting lines; and inactivating means responsive to outputs of said plurality of redundant circuit means for inactivating said plurality of first selecting means when a number of said plurality of redundant selecting lines are selected by any of said plurality of redundant circuit means.