Vector processor with a memory assigned with skewed addresses adapted for concurrent fetching of a number of vector elements belonging to the same vector data

Claim 2

A vector processor comprising: a storage for storing vector data therein including a plurality (M) of memory modules; a plurality (N) of requesters for concurrently issuing access requests for a plurality (N) of vector elements belonging to each of a plurality of concurrent element groups obtained by subdividing vector data stored in said storage, the value N being n times the value M, n being an integer greater than one, said requesters being divided into n requester groups; a plurality of (n) storage control units each disposed in correspondence to one of said requester groups, each storage control unit being connected to said memory modules and to plural requesters belonging to a corresponding one of said requester groups, each storage control unit transferring a plurality of access requests concurrently supplied from plural requesters belonging to said corresponding requester group to one or plural ones of said memory modules to which addresses contained in the access requests belong, each storage control unit concurrently transferring plural ones among a plurality of access requests supplied thereto, which plural ones contain addresses respectively belonging to mutually different ones of said memory modules, to said different memory modules and sequentially transferring plural ones of a plurality of access requests supplied thereto, which plural ones contain addresses belonging to an identical one of said memory modules, to said identical memory module; each memory module including plural memory bank groups and a plurality of access circuits each provided in correspondence to one of said memory bank groups, said memory bank groups including memory banks assigned with mutually different addresses, a total number of the memory bank groups being not less than the number (n) of said plurality of storage control units.

Claim 3

A vector processor according to claim 1, wherein: each memory module further includes a plurality of request queue groups each corresponding to one of said plural memory bank groups included in said each memory module, each request queue group including a plurality of request queues respectively connected to said plural storage control units and to one of said access circuits disposed in association with one of said memory bank groups corresponding to said each request queue group, said request queues being disposed respectively in association with said plural storage control units, each request queue in each said request queue group temporarily retaining an access request supplied from one of said storage control units associated with each request queue until the supplied access request is accepted by said associated access circuit.

Claim 4

A vector processor comprising: a storage for storing vector data therein including a plurality (M) of memory modules; a plurality (N) of requesters for concurrently issuing access requests for a plurality (N) of vector elements belonging to each of a plurality of concurrent element groups obtained by subdividing vector data stored in said storage, the value N being n times the value M, n being an integer greater than one, said requesters being divided into n requester groups; a plurality of (n) storage control units each disposed in correspondence to one of said requester groups each storage control unit being connected to said memory modules and to plural requesters belonging to a corresponding one of said requester groups, each storage control unit transferring a plurality of access requests concurrently supplied from plural requesters belonging to said corresponding requester group to one or plural ones of said memory modules to which addresses contained in the access requests belong, each storage control unit concurrently transferring plural ones among a plurality of access requests supplied thereto, which plural ones contain addresses respectively belonging to mutually different ones of said memory modules, to said different memory modules and sequentially transferring plural ones of a plurality of access requests supplied thereto, which plural ones contain addresses belonging to an identical one of said memory modules to said identical memory module, each memory module including plural memory bank groups and an access circuit connected to said plural storage control units and to said memory bank groups within said each memory module, said memory bank groups respectively assigned with mutually different addresses, a total number of the memory bank groups being not less than a number (n) of said plurality of storage control units, said access circuit transferring each of a plurality of access requests concurrently supplied thereto from said plurality of storage control units to one of said memory bank groups to which an address included in said each access request belongs; wherein said plural memory modules are assigned with addresses in such a manner that successive addresses are sequentially assigned to different ones of said memory modules in accordance with a predetermined sequence of memory modules, and are assigned, for every first predetermined number of addresses, to one of said memory modules different from one of said memory modules determined according to the sequence of memory modules.

Claim 5

A vector processor comprising: a storage for storing vector data therein including a plurality (M) of memory modules; a plurality (N) of requesters for concurrently issuing access requests for a plurality (N) of vector elements belonging to each of a plurality of concurrent element groups obtained by subdividing vector data stored in said storage, the value N being n times the value M, n being an integer greater than one, said requesters being divided into n requester groups; a plurality of (n) storage control units each disposed in correspondence to one of said requester groups each storage control unit being connected to said memory modules and to plural requesters belonging to a corresponding one of said requester groups, each storage control unit transferring a plurality of access requests concurrently supplied from plural requesters belonging to said corresponding requester group to one or plural ones of said memory modules to which addresses contained in the access requests belong, each storage control unit concurrently transferring plural ones among a plurality of access requests supplied thereto, which plural ones contain addresses respectively belonging to mutually different ones of said memory modules, to said different memory modules and sequentially transferring plural ones of a plurality of access requests supplied thereto, which plural ones contain addresses belonging to an identical one of said memory modules to said identical memory module, each memory module including plural memory bank groups and an access circuit connected to said plural storage control units and to said memory bank groups within said each memory module, said memory bank groups respectively assigned with mutually different addresses, a total number of the memory bank groups being not less than a number (n) of said plurality of storage control units, said access circuit transferring each of a plurality of access requests concurrently supplied thereto from said plurality of storage control units to one of said memory bank groups to which an address included in said each access request belongs; wherein said plural memory modules are assigned with addresses in such a manner that successive addresses are sequentially assigned to different ones of said memory modules in accordance with a predetermined sequence of memory modules, and are assigned, for every first predetermined number of addresses, to one of said memory modules different from one of said memory modules determined according to the sequence of memory modules.

Claim 6

A vector processor according to claim 3, wherein: each storage control unit includes: a plurality of priority units each disposed in association with and connected to one of said plural memory modules, each priority unit selecting one of a plurality of access requests supplied thereto and transmitting the selected access request to a memory module corresponding thereto; and a plurality of request send-out units each disposed in association with and connected to one of said requesters belonging to a requester group corresponding to said each storage control unit for judging one of the memory modules to which addresses respectively contained in the access requests respectively supplied from said requesters associated therewith respectively belong and for transmitting the access requests to said priority units respectively disposed in association with said memory modules, each of said priority units including: a plurality of request queues each disposed in association with and connected to one of said plural request send-out units for temporarily holding access requests transmitted from said request send-out units respectively associated therewith to each of said priority units; and a priority logic for selecting one of the plural access requests held in said plural request queues and transferring the selected access request to one of said memory modules corresponding to each priority, unit; each request send-out unit including: means for judging a memory module to which an address contained in the access request supplied from said associated requester belongs; and means connected to said judging means for controlling, in accordance with whether or not an empty area exists in a request queue disposed in one of said priority units related to said judged memory module, whether or not the access request is to be transmitted to said priority units disposed in association with said judged memory module.

Claim 7

A vector processor according to claim 4, wherein: the first predetermined number is not less than a total number of said memory bank groups included in said plural memory modules.

Claim 8

A vector processor according to claim 5, wherein: said plural bank groups within each memory module is assigned with a plurality of addresses assigned to said each memory module in such a manner that the plurality of addresses are sequentially assigned to different ones of said bank groups in a predetermined sequence of bank groups, and are assigned for every second predetermined number of addresses, to one of said bank groups different from one of said bank groups determined according to the sequence of bank groups.

Claim 9

A vector processor according to claim 6, wherein: the second predetermined number is identical to a value obtained as a quotient by dividing by a total number of said memory modules a result attained by multiplying the total number of said memory bank groups included in said plural memory modules by a quotient attained by dividing the first predetermined number by the number of said storage control units.

Claim 10

A vector processor according to claim 7, wherein: said plural banks belonging to each bank group within each memory module are assigned with a plurality of addresses assigned to said plural banks in such a manner that the plurality of addresses are sequentially assigned to different ones of said banks in a predetermined sequence of banks, and are assigned for every third predetermined number of addresses, to one of said banks different from one of said banks determined according to the sequence of banks.

Claim 11

A vector processor according to claim 8, wherein: the third predetermined number is identical to a value of a quotient attained by dividing the first predetermined number by the number of said plural storage control units.

Claim 12

A vector processor according to claim 3, wherein: each storage control unit includes: a plurality of priority units each disposed in association with and connected to one of said plural memory modules, each priority unit selecting one of a plurality of access requests supplied thereto for transmitting the selected access request to one of said memory modules corresponding thereto; and a plurality of request send-out units each disposed in association with and connected to one of said requesters belonging to one of said requester groups corresponding to each storage control unit for judging memory modules to which addresses respectively contained in the access requests respectively supplied from said requesters associated therewith respectively belong and for transmitting the access requests to said priority units respectively disposed in association with said memory modules, each priority unit selecting one of the plural access requests sent from said plural request send-out units thereto and transferring the selected access request to one of said memory modules corresponding to each priority unit, each request send-out unit judging one of said memory modules to which an address contained in the access request supplied from said associated requester belongs and transmitting the access request to one of said priority units disposed in association with said judged memory module, and each request send-out unit further controlling, in accordance with whether or not the transmitted access request is selected by said one priority unit, whether or not an access request subsequently supplied from said associated requester is to be transmitted to said one priority unit.

Claim 13

A vector processor according to claim 10, wherein: the first predetermined number is identical to the number of said plural memory modules.

Claim 14

A vector processor according to claim 11, wherein: said plural bank groups within each memory module is assigned with a plurality of addresses assigned to said each memory module in such a manner that the plurality of addresses are sequentially assigned to different ones of said bank groups in a predetermined sequence of bank groups, and are assigned for every second predetermined number of addresses, to one of said bank groups different from one of said bank groups determined according to the sequence of bank groups.

Claim 15

A vector processor according to claim 12, wherein: the second predetermined number is identical to a value obtained as a quotient by dividing by a total number of said memory modules a result attained by multiplying the total number of said memory bank groups included in said plural memory modules by a quotient attained by dividing the first predetermined number by the number of said storage control units.

Claim 16

A vector processor according to claim 13, wherein: said plural banks belonging to each bank group within each memory module are assigned with a plurality of addresses assigned to said plural banks in such a manner that the plurality of addresses are sequentially assigned to different ones of said banks in a predetermined sequence of banks, and are assigned for every third predetermined number of addresses, to one of said banks different from one of said banks determined according to the sequence of banks.

Claim 17

A vector processor according to claim 14, wherein: the third predetermined number is identical to a value of a quotient attained by dividing the first predetermined number by the number of said plural storage control units.

Claim 18

A vector processor according to claim 3, wherein: the first predetermined number is not less than a total number of said memory bank groups included in said plural memory modules.

Claim 19

A vector processor according to claim 16, wherein: said plural bank groups within each memory module is assigned with a plurality of addresses assigned to said each memory module in such a manner that the plurality of addresses are sequentially assigned to different ones of said bank groups in a predetermined sequence of bank groups, and are assigned for every second predetermined number of addresses, to one of said bank groups different from one of said bank groups determined according to the sequence of bank groups.

Claim 20

A vector processor according to claim 17, wherein: the second predetermined number is identical to a value obtained as a quotient by dividing by a total number of said memory modules a result attained by multiplying the total number of said memory bank groups included in said plural memory modules by a quotient attained by dividing the first predetermined number by the number of said storage control units.

Claim 21

A vector processor according to claim 18, wherein: said plural banks belonging to each bank group within each memory module are assigned with a plurality of addresses assigned to said plural banks in such a manner that the plurality of addresses are sequentially assigned to different ones of said banks in a predetermined sequence of banks, and are assigned for every third predetermined number of addresses, to one of said banks different from one of said banks determined according to the sequence of banks.

Claim 22

A vector processor according to claim 19, wherein: the third predetermined number is identical to a value of a quotient attained by dividing the first predetermined number by the number of said plural storage control units.

Claim 23

A vector processor according to claim 3, wherein: the first predetermined number is identical to the number of said plural memory modules.

Claim 24

A vector processor according to claim 21, wherein: said plural bank groups within each memory module is assigned with a plurality of addresses assigned to said each memory module in such a manner that the plurality of addresses are sequentially assigned to different ones of said bank groups in a predetermined sequence of bank groups, and are assigned for every second predetermined number of addresses, to one of said bank groups different from one of said bank groups determined according to the sequence of bank groups.

Claim 25

A vector processor according to claim 22, wherein: the second predetermined number is identical to a value obtained as a quotient by dividing by a total number of said memory modules a result attained by multiplying the total number of said memory bank groups included in said plural memory modules by a quotient attained by dividing the first predetermined number by the number of said storage control units.

Claim 26

A vector processor according to claim 23, wherein: said plural banks belonging to each bank group within each memory module are assigned with a plurality of addresses assigned to said plural banks in such a manner that the plurality of addresses are sequentially assigned to different ones of said banks in a predetermined sequence of banks, and are assigned for every third predetermined number of addresses, to one of said banks different from one of said banks determined according to the sequence of banks.

Claim 27

A vector processor according to claim 24, wherein: the third predetermined number is identical to a value of a quotient attained by dividing the first predetermined number by the number of said plural storage control units.

Claim 28

A vector processor comprising: a storage for storing vector data therein including a plurality (M) of memory modules; a plurality (N) of requesters for concurrently issuing access requests for a plurality (N) of vector elements belonging to each of a plurality of concurrent element groups obtained by subdividing vector data stored in said storage, the value N being n times the value M, n being an integer greater than one, said requesters being divided into n requester groups; a plurality of (n) storage control units each disposed in correspondence to one of said requester groups, each storage control unit being connected to said memory modules and to plural requesters belonging to a corresponding one of said requester groups, each storage control unit transferring a plurality of access requests concurrently supplied from plural requesters belonging to said corresponding requester group to one or plural ones of said memory modules to which addresses contained in the access requests belong; each storage control unit concurrently transferring plural ones among a plurality of access requests supplied thereto, which plural ones contain addresses respectively belonging to mutually different ones of said memory modules to said different memory modules and sequentially transferring plural ones of a plurality of access requests supplied thereto, which plural ones contain addresses belonging to an identical one of said memory modules, to said identical memory module, each memory module including: plural memory bank groups, and an access circuit connected to said plurality of storage control units and to said memory bank groups within said each memory module, said memory bank groups being assigned with mutually different addresses, a total number of the memory bank groups being not less than a number (n) of said plurality of storage control units, said access circuit transferring each of a plurality of access requests concurrently supplied thereto from said plurality of storage control units to one of said memory bank groups to which an address included in said each access request belongs, wherein: each requester belongs to a requester group having a serial number equal to a value of a remainder attained by dividing an element number (a) within a concurrent element group, assigned to an element for which said each requester is to issue a request, by a total number (n) of said requester groups.

Claim 29

A vector processor comprising: a storage for storing vector data therein including a plurality (M) of memory modules; a plurality (N) of requesters for concurrently issuing access requests for a plurality (N) of vector elements belonging to each of a plurality of concurrent element groups obtained by subdividing vector data stored in said storage, the value N being n times the value M, n being an integer greater than one, said requesters being divided into n requester groups; a plurality of (n) storage control units each disposed in correspondence to one of said requester groups, each storage control unit being connected to said memory modules and to plural requesters belonging to a corresponding one of said requester groups, each storage control unit transferring a plurality of access requests concurrently supplied from plural requesters belonging to said corresponding requester group to one or plural ones of said memory modules to which addresses contained in the access requests belong; each storage control unit concurrently transferring plural ones among a plurality of access requests supplied thereto, which plural ones contain addresses respectively belonging to mutually different ones of said memory modules to said different memory modules and sequentially transferring plural ones of a plurality of access requests supplied thereto, which plural ones contain addresses belonging to an identical one of said memory modules, to said identical memory module, each memory module including: plural memory bank groups, and an access circuit connected to said plurality of storage control units and to said memory bank groups within said each memory module, said memory bank groups being assigned with mutually different addresses, a total number of the memory bank groups being not less than a number (n) of said plurality of storage control units, said access circuit transferring each of a plurality of access requests concurrently supplied thereto from said plurality of storage control units to one of said memory bank groups to which an address included in said each access request belongs, wherein: each requester belongs to a requester group having a serial number equal to a value of a remainder attained by dividing an element number (a) within a concurrent element group, assigned to an element for which said each requester is to issue a request, by a total number (n) of said requester groups.

Claim 30

A vector processor according to claim 26, wherein: said plural memory modules are assigned with addresses in such a manner that successive addresses are sequentially assigned to different ones of said memory modules in accordance with a predetermined sequence of memory modules, and are assigned, for every first predetermined number of addresses, to one of said memory modules different from a memory module determined according to the sequence of memory modules.

Claim 31

A vector processor according to claim 27, wherein: the first predetermined number is not less than a total number of said memory bank groups included in said plural memory modules.

Claim 32

A vector processor according to claim 28, wherein: said plural bank groups within each memory module is assigned with a plurality of addresses assigned to said each memory module in such a manner that the plurality of addresses are sequentially assigned to different ones of said bank groups in a predetermined sequence of bank groups, and are assigned, for every second predetermined number of addresses, to one of said bank groups different from one of said bank groups determined according to the sequence of bank groups.

Claim 33

A vector processor according to claim 29, wherein: the second predetermined number is identical to a value obtained as a quotient by dividing by a total number of said memory modules a result attained by multiplying the total number of said memory bank groups included in said plural memory modules by a quotient attained by dividing the first predetermined number by the number of said storage control units.

Claim 34

A vector processor according to claim 30, wherein: said plural banks belonging to each bank group within each memory module are assigned with a plurality of addresses assigned to said plural banks in such a manner that the plurality of addresses are sequentially assigned to different ones of said banks in a predetermined sequence of banks, and are assigned, for every third predetermined number of addresses, to one of said banks different from one of said banks determined according to the sequence of banks.

Claim 35

A vector processor according to claim 31, wherein: the third predetermined number is identical to a value of a quotient attained by dividing the first predetermined number by the number of said plural storage control units.

Claim 36

A vector processor according to claim 27, wherein: the first predetermined number is identical to the number of said plural memory modules.

Claim 37

A vector processor according to claim 33, wherein: said plural bank groups within each memory module are assigned with a plurality of addresses assigned to said each memory module in such a manner that the addresses are sequentially assigned to different ones of said bank groups in a predetermined sequence of bank groups, and are assigned, for every second predetermined number of addresses, to one of said bank groups different from one of said bank groups determined according to the sequence of bank groups.

Claim 38

A vector processor according to claim 34, wherein: the second predetermined number is identical to a value obtained as a quotient by dividing by a total number of said memory modules a result attained by multiplying the total number of said memory bank groups included in said plural memory modules by a quotient attained by dividing the first predetermined number by the number of said storage control units.

Claim 39

A vector processor according to claim 35, wherein: said plural banks belonging to each said bank group are assigned with a plurality of addresses assigned to said each memory module in such a manner that the addresses are sequentially assigned to different ones of said banks in a predetermined sequence of banks, and are assigned, for every third predetermined number of, to one of said banks different from one of said banks determined according to the sequence of banks.

Claim 40

A vector processor according to claim 36, wherein: the third predetermined number is identical to a value of a quotient attained by dividing the first predetermined number by the number of said plural storage control units.

Claim 41

A vector processor comprising: a storage for storing vector data therein, including a plurality (M) of memory modules; a plurality (N) of requesters for concurrently issuing access requests for a plurality (N) of vector elements belonging to each of a plurality of concurrent element groups obtained by subdividing vector data stored in said storage; a storage control unit connected to the requesters for transferring a plurality of access requests concurrently supplied from said plural requesters to one or ones of said memory modules to which addresses respectively contained in the access requests belong, said plural memory modules being sequentially assigned with addresses in such a manner that successive addresses are assigned to different ones of said memory modules, determined according to a first predetermined sequence of memory modules and are assigned, for every first predetermined number of addresses, to one of said memory modules different from one of said memory modules determined according to the sequence of memory modules, said storage control unit including: a plurality of priority units each disposed in association with and connected to one of said plural memory modules, each priority unit selecting one of a plurality of access requests supplied to said each priority unit and transmitting the selected access request to a corresponding one of the memory modules; and a plurality of request send-out units each disposed in association with and connected to one of said requesters belonging to one of said requester groups corresponding to each storage control unit for judging ones of said memory modules to which addresses respectively contained in the access requests respectively supplied from said requesters associated therewith respectively belong and for transmitting the access requests to said priority units respectively disposed in association with said judged memory modules, each priority unit including: a plurality of request queues each disposed in association with and connected to one of said plural request send-out units for temporarily holding access requests transmitted from said request send-out units respectively associated therewith to each priority unit; and means for selecting one of the plural access requests held in said plural request queues and transferring the access request to a memory module corresponding to each priority unit, each request send-out unit including: means for judging a memory module to which an address contained in the access request supplied from said associated requester belongs; and means for controlling, in accordance with whether or not an empty area exists in a request queue disposed in a priority unit related to said judged memory module, whether or not the access request is to be transmitted to said priority unit disposed in association with said judged memory module.

Claim 42

A vector processor comprising: a storage for storing vector data therein, including a plurality (M) of memory modules; a plurality (N) of requesters for concurrently issuing access requests for a plurality (N) of vector elements belonging to each of a plurality of concurrent element groups obtained by subdividing vector data stored in said storage; a storage control unit connected to the requesters for transferring a plurality of access requests concurrently supplied from said plural requesters to one or ones of said memory modules to which addresses respectively contained in the access requests belong, said plural memory modules being sequentially assigned with addresses in such a manner that successive addresses are assigned to different ones of said memory modules, determined according to a first predetermined sequence of memory modules and are assigned, for every first predetermined number of addresses, to one of said memory modules different from one of said memory modules determined according to the sequence of memory modules, said storage control unit including: a plurality of priority units each disposed in association with and connected to one of said plural memory modules, each priority unit selecting one of a plurality of access requests supplied to said each priority unit and transmitting the selected access request to a corresponding one of the memory modules; and a plurality of request send-out units each disposed in association with and connected to one of said requesters belonging to one of said requester groups corresponding to each storage control unit for judging ones of said memory modules to which addresses respectively contained in the access requests respectively supplied from said requesters associated therewith respectively belong and for transmitting the access requests to said priority units respectively disposed in association with said judged memory modules, each priority unit including: a plurality of request queues each disposed in association with and connected to one of said plural request send-out units for temporarily holding access requests transmitted from said request send-out units respectively associated therewith to each priority unit; and means for selecting one of the plural access requests held in said plural request queues and transferring the access request to a memory module corresponding to each priority unit, each request send-out unit including: means for judging a memory module to which an address contained in the access request supplied from said associated requester belongs; and means for controlling, in accordance with whether or not an empty area exists in a request queue disposed in a priority unit related to said judged memory module, whether or not the access request is to be transmitted to said priority unit disposed in association with said judged memory module.

Claim 43

A vector processor according to claim 38, wherein: the first predetermined number is not less than a total number of said memory bank groups included in said plural memory modules.

Claim 44

A vector processor according to claim 39, wherein: said plural bank groups within each memory module is assigned with a plurality of addresses assigned to said each memory module in such a manner that the plurality of addresses are sequentially assigned to different ones of said bank groups in a predetermined sequence of bank groups, and are assigned for every second predetermined number of addresses, to one of said bank groups different from one of said bank groups determined according to the sequence of bank groups.

Claim 45

A vector processor according to claim 40, wherein: the second predetermined number is identical to a value obtained as a quotient by dividing by a total number of said memory modules a result attained by multiplying the total number of said memory bank groups included in said plural memory modules by a quotient attained by dividing the first predetermined number by the number of said storage control unit.

Claim 46

A vector processor according to claim 41, wherein: said plural banks belonging to each bank group within each memory module are assigned with a plurality of addresses assigned to said plural banks in such a manner that the plurality of addresses are sequentially assigned to different ones of said banks in a predetermined sequence of banks, and are assigned for every third predetermined number of addresses, to one of said banks different from one of said banks determined according to the sequence of banks.

Claim 47

A vector processor according to claim 42, wherein: the third predetermined number is identical to a value of a quotient attained by dividing the first predetermined number by the number of said plural storage control unit.