US5393233A
Expired / Lapsed
US
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Process for fabricating double poly high density buried bit line mask ROM
Assignee: United Microelectronics Corp
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Filing: 1993-07-14
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Granted: 1995-02-28
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Expires: 2013-07-14
Abstract
Abstract In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.
Inventors
- 👤 Gary Hong
- 👤 Ming-Tzong Yang
- 👤 Chen-Chiu Hsue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:09
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
233 words
A method of producing a Read Only Memory device comprising a substrate, buried bit lines formed in the substrate and two sets of poly word lines forms on the substrate, said method comprising the steps of (a) providing a semiconductor substrate of a first conductivity type having buried bit lines of a second conductivity type; (b) depositing a first gate oxide layer on the substrate; (c) depositing a nitride layer on the substrate and selectively etching the nitride layer to define a mark and spaced apart nitride lines; (d) performing a first code implantation in selected openings between the nitride lines; (e) depositing a first polysilicon layer on the substrate and chemical-mechanical polishing the first polysilicon layer using the nitride mark and nitride lines as a stop to form a first set of polysilicon word lines between the nitride lines; (f) removing the nitride lines but not the nitride mark; (g) performing a second code implantation in selected ones of the openings formed by the removal of the nitride lines; (h) forming a second gate oxide layer on the substrate and on the surfaces of the first set of polysilicon lines; (i) depositing a second layer of polysilicon on the substrate and chemical-mechanical polishing the second polysilicon layer using the nitride mark as a stop to form a second set of polysilicon word lines in between the first set of polysilicon word lines.
Claim 2
Independent Claim
233 words
A method of producing a Read Only Memory device comprising a substrate, buried bit lines formed in the substrate and two sets of poly word lines forms on the substrate, said method comprising the steps of (a) providing a semiconductor substrate of a first conductivity type having buried bit lines of a second conductivity type; (b) depositing a first gate oxide layer on the substrate; (c) depositing a nitride layer on the substrate and selectively etching the nitride layer to define a mark and spaced apart nitride lines; (d) performing a first code implantation in selected openings between the nitride lines; (e) depositing a first polysilicon layer on the substrate and chemical-mechanical polishing the first polysilicon layer using the nitride mark and nitride lines as a stop to form a first set of polysilicon word lines between the nitride lines; (f) removing the nitride lines but not the nitride mark; (g) performing a second code implantation in selected ones of the openings formed by the removal of the nitride lines; (h) forming a second gate oxide layer on the substrate and on the surfaces of the first set of polysilicon lines; (i) depositing a second layer of polysilicon on the substrate and chemical-mechanical polishing the second polysilicon layer using the nitride mark as a stop to form a second set of polysilicon word lines in between the first set of polysilicon word lines.
Claim 3
Independent Claim
119 words
A method for producing a buried bit line Read Only Memory device comprising the steps of depositing a first layer of polysilicon material on a surface of a semiconductor substrate with buried bit lines and having mask lines and a mark and chemical-mechanical polishing the first layer of polysilicon material using the mask lines and mark as a stop to form a first set of polysilicon word lines oriented orthogonally to said buried bit lines, removing said mask lines, depositing a second layer of polysilicon material and chemical-mechanical polishing the second layer of polysilicon material using the mark as a stop to form a second set of polysilicon word lines in between said first set of polysilicon word lines.
Claim 4
Independent Claim
119 words
A method for producing a buried bit line Read Only Memory device comprising the steps of depositing a first layer of polysilicon material on a surface of a semiconductor substrate with buried bit lines and having mask lines and a mark and chemical-mechanical polishing the first layer of polysilicon material using the mask lines and mark as a stop to form a first set of polysilicon word lines oriented orthogonally to said buried bit lines, removing said mask lines, depositing a second layer of polysilicon material and chemical-mechanical polishing the second layer of polysilicon material using the mark as a stop to form a second set of polysilicon word lines in between said first set of polysilicon word lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |