US5394171A
Expired / Lapsed
US
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Synchronizing signal front end processor for video monitor
Assignee: Zenith Electronics LLC
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Filing: 1992-11-02
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Granted: 1995-02-28
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Expires: 2012-11-02
Abstract
Abstract A synchronizing signal front end processor for video monitors includes a synchronizing signal subprocessor which responds to computer generated horizontal and vertical rate scan signals to provide alternative scan signal coupling in the event of interruption or abnormalities of the applied scan signals. The processor also includes horizontal and vertical synchronizing signal subprocessors which produce output signals indicative of the polarity and frequency of the applied selected scan synchronizing signals. In addition, the vertical and horizontal sync subprocessors provide respective sync out of range signals during sync interruption or abnormality which are utilized to stabilize the monitor display scanning process while switching to alternative scan synchronizing signal sources. The horizontal and vertical sync subprocessors each utilize a counter controlled by an edge detection system to accumulate clock signal count numbers indicative of the positive and negative portions of the applied scan synchronizing signals. These counts are utilized for polarity decoding and frequency decoding within the system.
Inventors
- 👤 Khosro M. Rabii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:27
CPC Classifications
G; G09; G09G; G09G1/00; G09G1/06; G09G1/14; G09G1/16; G09G1/165; G09G1/167
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
130 words
For use in a display system responsive to display scan synchronizing signals having polarity and frequency encoded information, a method of scan synchronizing signal processing comprising the steps of: receiving scan synchronizing signals; detecting edge portions within said scan synchronizing signal; producing a plurality of successive numeric counts representing the successive portions of said scan synchronizing signal between successive edge portions; comparing one of said numeric counts to its directly preceding numeric count to determine scan synchronizing signal polarity; and combining a successive pair of said numeric counts to determine scan synchronizing signal frequency, said detecting step including the steps of: generating a rising edge signal each time a rising edge portion is detected; and generating an edge signal each time either a rising or falling edge portion is detected.
Claim 2
Dependent Claim
130 words
For use in a display system responsive to display scan synchronizing signals having polarity and frequency encoded information, a method of scan synchronizing signal processing comprising the steps of: receiving scan synchronizing signals; detecting edge portions within said scan synchronizing signal; producing a plurality of successive numeric counts representing the successive portions of said scan synchronizing signal between successive edge portions; comparing one of said numeric counts to its directly preceding numeric count to determine scan synchronizing signal polarity; and combining a successive pair of said numeric counts to determine scan synchronizing signal frequency, said detecting step including the steps of: generating a rising edge signal each time a rising edge portion is detected; and generating an edge signal each time either a rising or falling edge portion is detected.
Claim 3
Dependent Claim
62 words
The method of claim 1 wherein said step of producing a plurality of successive numeric counts includes the steps of: providing a periodic clock signal having a frequency substantially higher than that of said scan synchronizing signal; counting said clock signals; restarting said counting step in response to each edge signal to produce successive numeric counts; and storing said successive numeric counts.
Claim 4
Dependent Claim
25 words
The method of claim 2 wherein said combining step includes the step of adding a pair of successive numeric counts to produce a period count.
Claim 5
Dependent Claim
23 words
The method of claim 3 wherein said combining step further includes a step of converting said period count to a frequency indicative signal.
Claim 6
Dependent Claim
82 words
The method of claim 4 wherein said converting step includes the steps of: providing a downcounting clock signal having a numeric value which decreases from a predetermined start number greater than said numeric count on a repetitive basis to produce a downcounting number; comparing said period count to said downcounting number; and producing an output signal having a first condition so long as said downcounting number exceeds said period count and a second condition when it is less than said downcounting number.
Claim 7
Dependent Claim
21 words
The method of claim 1 wherein said comparing step includes timing said comparison to the occurrence of a detected rising edge.
Claim 8
Dependent Claim
137 words
For use in a display system responsive to display scan synchronizing signals having polarity and frequency encoded information, a scan synchronizing signal processor comprising: means for receiving scan synchronizing signals; means for detecting edge portions within said scan synchronizing signal; means for producing a plurality of successive numeric counts representing the successive portions of said scan synchronizing signal between successive edge portions; means for comparing one of said numeric counts to its directly preceding numeric count to determine scan synchronizing signal polarity; and means for combining a successive pair of said numeric counts to determine scan synchronizing signal frequency, said means for detecting including: means for generating a rising edge signal each time a rising edge portion is detected; and means for generating an edge signal each time either a rising or falling edge portion is detected.
Claim 9
Dependent Claim
137 words
For use in a display system responsive to display scan synchronizing signals having polarity and frequency encoded information, a scan synchronizing signal processor comprising: means for receiving scan synchronizing signals; means for detecting edge portions within said scan synchronizing signal; means for producing a plurality of successive numeric counts representing the successive portions of said scan synchronizing signal between successive edge portions; means for comparing one of said numeric counts to its directly preceding numeric count to determine scan synchronizing signal polarity; and means for combining a successive pair of said numeric counts to determine scan synchronizing signal frequency, said means for detecting including: means for generating a rising edge signal each time a rising edge portion is detected; and means for generating an edge signal each time either a rising or falling edge portion is detected.
Claim 10
Dependent Claim
73 words
A scan synchronizing signal processor as set forth in claim 7 wherein said means for producing a plurality of successive numeric counts includes: means for providing a periodic clock signal having a frequency substantially higher than that of said scan synchronizing signal; means for counting said clock signals; means for restarting said counting step in response to each edge signal to produce successive numeric counts; and means for storing said successive numeric counts.
Claim 11
Dependent Claim
31 words
A scan synchronizing signal processor as set forth in claim 8 wherein said means for combining includes: means for adding a pair of successive numeric counts to produce a period count.
Claim 12
Dependent Claim
29 words
A scan synchronizing signal processor as set forth in claim 9 wherein said means for combining further includes: means for converting said period count to a frequency indicative signal.
Claim 13
Dependent Claim
92 words
A scan synchronizing signal processor as set forth in claim 10 wherein said means for converting includes: means for providing a downcounting clock signal having a numeric value which decreases from a predetermined start number greater than said numeric count on a repetitive basis to produce a downcounting number; means for comparing said period count to said downcounting number; and means for producing an output signal having a first condition so long as said downcounting number exceeds said period count and a second condition when it is less than said downcounting number.
Claim 14
Dependent Claim
30 words
A scan synchronizing signal processor as set forth in claim 7 wherein said means for comparing includes means for timing said comparison to the occurrence of a detected rising edge.
Claim 15
Dependent Claim
160 words
For use in a display system responsive to display scan synchronizing signals having polarity and frequency encoded information, a method of scan synchronizing signal processing comprising the steps of: receiving scan synchronizing signals; detecting falling and rising edge portions within said scan synchronizing signal; producing a first numeric count representing the portion of said scan synchronizing signal between successive falling and rising edge portions; producing a second numeric count representing the portion of said scan synchronizing signal between successive rising and falling edge portions; comparing said first and second numeric counts to determine scan synchronizing signal polarity; and combining said first and second numeric counts to determine scan synchronizing signal frequency, said detecting step including the steps of: generating a rising edge signal each time a rising edge portion is detected; generating a falling edge signal each time a falling edge portion is detected; and generating an edge signal each time either a rising or falling edge portion is detected.
Claim 16
Dependent Claim
160 words
For use in a display system responsive to display scan synchronizing signals having polarity and frequency encoded information, a method of scan synchronizing signal processing comprising the steps of: receiving scan synchronizing signals; detecting falling and rising edge portions within said scan synchronizing signal; producing a first numeric count representing the portion of said scan synchronizing signal between successive falling and rising edge portions; producing a second numeric count representing the portion of said scan synchronizing signal between successive rising and falling edge portions; comparing said first and second numeric counts to determine scan synchronizing signal polarity; and combining said first and second numeric counts to determine scan synchronizing signal frequency, said detecting step including the steps of: generating a rising edge signal each time a rising edge portion is detected; generating a falling edge signal each time a falling edge portion is detected; and generating an edge signal each time either a rising or falling edge portion is detected.
Claim 17
Dependent Claim
85 words
The method of claim 13 wherein said steps of producing first and second numeric counts include the steps of: providing a periodic clock signal having a frequency substantially higher than that of said scan synchronizing signal; counting said clock signals; restarting said counting step in response to each edge signal; storing the clock signal count as said first numeric count in response to said rising edge signal; and storing the clock signal count as said second numeric count in response to said falling edge signal.
Claim 18
Dependent Claim
25 words
The method of claim 14 wherein said combining step includes the step of adding said first and second numeric counts to produce a period count.
Claim 19
Dependent Claim
23 words
The method of claim 15 wherein said combining step further includes a step of converting said period count to a frequency indicative signal.
Claim 20
Dependent Claim
74 words
The method of claim 16 wherein said converting step includes the steps of: downcounting said clock signal from a predetermined start number greater than said numeric count on a repetitive basis to producing downcount numbers; comparing said period count to said downcount numbers; and producing an output signal having a first condition so long as said downcount numbers exceed said period count and a second condition when it is less than said downcount numbers.
Claim 21
Dependent Claim
149 words
For use in a display system responsive to display scan synchronizing signals having polarity and frequency encoded information, a scan synchronizing signal processor comprising: means for receiving scan synchronizing signals; means for detecting falling and rising edge portions within said scan synchronizing signal; means for producing a first numeric count representing the portion of said scan synchronizing signal between successive falling and rising edge portions; means for comparing said first and second numeric counts to determine scan synchronizing signal polarity; and means for combining said first and second numeric counts to determine scan synchronizing signal frequency, said means for detecting including: means for generating a rising edge signal each time a rising edge portion is detected; means for generating a falling edge signal each time a falling edge portion is detected; and means for generating an edge signal each time either a rising or falling edge portion is detected.
Claim 22
Dependent Claim
149 words
For use in a display system responsive to display scan synchronizing signals having polarity and frequency encoded information, a scan synchronizing signal processor comprising: means for receiving scan synchronizing signals; means for detecting falling and rising edge portions within said scan synchronizing signal; means for producing a first numeric count representing the portion of said scan synchronizing signal between successive falling and rising edge portions; means for comparing said first and second numeric counts to determine scan synchronizing signal polarity; and means for combining said first and second numeric counts to determine scan synchronizing signal frequency, said means for detecting including: means for generating a rising edge signal each time a rising edge portion is detected; means for generating a falling edge signal each time a falling edge portion is detected; and means for generating an edge signal each time either a rising or falling edge portion is detected.
Claim 23
Dependent Claim
98 words
A scan synchronizing signal processor as set forth in claim 18 wherein said means for producing first and second numeric counts include: means for providing a periodic clock signal having a frequency substantially higher than that of said scan synchronizing signal; means for counting said clock signals; means for restarting said counting step in response to each edge signal; means for storing the clock signal count as said first numeric count in response to said rising edge signal; and means for storing the clock signal count as said second numeric count in response to said falling edge signal.
Claim 24
Dependent Claim
31 words
A scan synchronizing signal processor as set forth in claim 19 wherein said means for combining includes: means for adding said first and second numeric counts to produce a period count.
Claim 25
Dependent Claim
29 words
A scan synchronizing signal processor as set forth in claim 20 wherein said means for combining further includes: means for converting said period count to a frequency indicative signal.
Claim 26
Dependent Claim
84 words
A scan synchronizing signal processor as set forth in claim 21 wherein said means for converting includes: means for downcounting said clock signal from a predetermined start number greater than said numeric count on a repetitive basis to producing downcount numbers; means for comparing said period count to said downcount numbers; and means for producing an output signal having a first condition so long as said downcount numbers exceed said period count and a second condition when it is less than said downcount numbers.
References Cited (Backward Citations)
US4665495A
Cited
US4837621A
Cited
US5111190A
Cited
US5134481A
Cited
US5155595A
Cited
US5212552A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |