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US5394189A Expired / Lapsed US ⏱️ 0.0 years remaining

Motion picture coder and system for controlling the same

Assignee: NEC Corp
•
Filing: 1993-01-28
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Granted: 1995-02-28
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Expires: 2013-01-28
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Abstract

Abstract A motion picture coder for coding plural macro blocks of motion picture data based on a standardizing system is disclosed. The coder comprises first and second pipe-lined processors executing different coding processes respectively, both of which are separated from one another so as to accomplish a parallel operation thereof. The first processor executes a motion vector detection for a second macro block, an inter-frame addition for a first macro block and an inter-frame difference for the first macro block. The second processor executes a discrete cosine transform for the first macro block, a quantization for the first macro block, an inverse quantization for the first macro block, an inverse discrete cosine transform for the first macro block and a loop filtering for the second macro block. The motion vector detection and the discrete cosine transform are concurrently processed and the inter-frame addition and the loop filtering are concurrently processed, thereby the processing times for each macro block are shortened and thus a high speed processing is realized.

Inventors

  • 👤 Masato Motomura
  • 👤 Tadayoshi Enomoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 07:39
CPC Classifications
H; H04; H04N; H04N19/00; H04N19/42; H04N19/60; H04N19/61

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 142 words
A motion picture coder having multi-pipeline stages for coding a plurality of macro blocks of motion picture data based upon a predetermined standardizing system, said coder comprising: a first pipe-lined processor for executing a motion vector detection process for a second macro block, an inter-frame addition process for a first macro block and an inter-frame difference process for said second macro block; and a second pipe-lined processor for executing a discrete cosine transform process for said first macro block, a quantization process for said first macro block, an inverse quantization process for said first macro block, an inverse discrete cosine transform process for said first macro block and a loop filtering process for said first macro block, said second pipe-lined processor being separated from said first pipe-lined processor so as to perform a parallel operation of said first and second pipe-lined processors.
Claim 2
Dependent Claim 142 words
A motion picture coder having multi-pipeline stages for coding a plurality of macro blocks of motion picture data based upon a predetermined standardizing system, said coder comprising: a first pipe-lined processor for executing a motion vector detection process for a second macro block, an inter-frame addition process for a first macro block and an inter-frame difference process for said second macro block; and a second pipe-lined processor for executing a discrete cosine transform process for said first macro block, a quantization process for said first macro block, an inverse quantization process for said first macro block, an inverse discrete cosine transform process for said first macro block and a loop filtering process for said first macro block, said second pipe-lined processor being separated from said first pipe-lined processor so as to perform a parallel operation of said first and second pipe-lined processors.
Claim 3
Dependent Claim 30 words
The motion picture coder as claimed in claim 1, wherein said first and second pipe-lined processors concurrently execute said motion vector detection process and said discrete cosine transform process respectively.
Claim 4
Dependent Claim 28 words
The motion picture coder as claimed in claim 1, wherein said first and second pipe-lined processors concurrently execute said inter-frame addition process and said loop filtering process respectively.
Claim 5
Dependent Claim 45 words
The motion picture coder as claimed in claim 1, wherein said first pipe-lined processor comprises first, second and third pipe-lined stages, said first pipe-lined stage including an adder, said second pipe-lined stage including an accumulator and said third pipe-lined stage including a minimum value detector.
Claim 6
Dependent Claim 35 words
The motion picture coder as claimed in claim 1, wherein said second pipe-lined processor comprises first and second pipe-lined stages, said first pipe-lined stage including a multiplier and said second pipe-lined stage including an accumulator.

References Cited (Backward Citations)

US5054103A Cited
US5057918A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-02-27 1998-08-29 1999-02-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-02-27 2002-08-29 2003-02-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-02-27 2006-08-29 2007-02-28 $7700.00 Window Closed / Lapsed

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