Decoding circuit for variable length code

Claim 2

A variable length code decoding circuit comprising: a shift register storing a bit sequence of variable bit length code variable of number of bits; decoding table storage means for storing data including an upper field selectively indicative of a meaning of the code and an address for next access, selected depending upon a state transition upon decoding said variable bit length code per n bits, in which n is an integer greater than or equal to two, an intermediate field indicative of a shifting magnitude of said shift register upon completion of decoding, and a lower field indicative of a state of code decoding; a shift control means for shifting said bit sequence of said variable bit length code in a magnitude corresponding to a shifting magnitude indicated in said intermediate field when data indicative of the code decoding state in said lower field of the data read out from said decoding table storage means indicates completion of decoding and corresponding to n bits when said data indicative of the code decoding state in said lower field indicates continuation of decoding; and means for generating an address for accessing said decoding table storage means by replacing said intermediate field and said lower field of data read out from said decoding table storage means with leading n bits of said shift register.

Claim 3

A variable length code decoding circuit as set forth in claim 1, wherein said lower field of said decoding table storage means is data of one bit.

Claim 4

A variable length code decoding circuit as set forth in claim 1, which further comprises an initial data register for storing one specific data having the same structure to the data stored in said decoding table storage means and providing said specific data to said address generating means in place of the data read out from said decoding table storage means upon initiation of decoding of said code.

Claim 5

A variable length code decoding circuit as set forth in claim 1, which further comprises an end data register for storing the content of said upper field of the read out data as a result of decoding when the data indicative of the code decoding state in the lower field of the data read out from said decoding table storage means indicates completion of decoding.

Claim 6

A variable length code decoding circuit comprising: a shift register storing a bit sequence of variable bit length code variable of number of bits; decoding table storage means for storing data including an upper field selectively indicative of a meaning of the code and an address for next access, selected depending upon a state transition upon decoding said variable bit length code per n bits which n is an integer greater than or equal to two, an intermediate field indicative of a shifting magnitude of said shift register upon completion of decoding, and a lower field indicative of a state of code decoding, said upper and intermediate field containing data indicative of an address for next access, and a plurality of said being divided into blocks of a size of 2 n and blocks of lesser size; a shift control means for shifting said bit sequence of said variable bit length code in a magnitude corresponding to a shifting magnitude indicated in said intermediate field when data indicative of the code decoding state in said lower field of the data read out from said decoding table storage means indicates completion of decoding and corresponding to n bits when said data indicative of the code decoding state in said lower field indicates continuation of decoding; and address designating means for selecting number of bits for designating address in said block depending upon the size of block on the basis of leading n bits of said shift register; and means for generating an address for accessing said decoding table storage means by replacing the lower bits of said upper field and said intermediate field of data read out from said decoding table storage means with leading n bits of said shift register.

Claim 7

A variable length code decoding circuit comprising: a shift register storing a bit sequence of variable bit length code variable of number of bits; decoding table storage means for storing data including an upper field selectively indicative of a meaning of the code and an address for next access, selected depending upon a state transition upon decoding said variable bit length code per n bits which n is an integer greater than or equal to two, an intermediate field indicative of a shifting magnitude of said shift register upon completion of decoding, and a lower field indicative of a state of code decoding, said upper and intermediate field containing data indicative of an address for next access, and a plurality of said being divided into blocks of a size of 2 n and blocks of lesser size; a shift control means for shifting said bit sequence of said variable bit length code in a magnitude corresponding to a shifting magnitude indicated in said intermediate field when data indicative of the code decoding state in said lower field of the data read out from said decoding table storage means indicates completion of decoding and corresponding to n bits when said data indicative of the code decoding state in said lower field indicates continuation of decoding; and address designating means for selecting number of bits for designating address in said block depending upon the size of block on the basis of leading n bits of said shift register; and means for generating an address for accessing said decoding table storage means by replacing the lower bits of said upper field and said intermediate field of data read out from said decoding table storage means with leading n bits of said shift register.

Claim 8

A variable length code decoding circuit as set forth in claim 5, which further comprises an initial data register for storing one specific data having the same structure to the data stored in said decoding table storage means and providing said specific data to said address generating means in place of the data read out from said decoding table storage means upon initiation of decoding of said code.

Claim 9

A variable length code decoding circuit as set forth in claim 5, which further comprises an end data register for storing the content of said upper field of the read out data as a result of decoding when the data indicative of the code decoding state in the lower field of the data read out from said decoding table storage means indicates completion of decoding.

Claim 10

A variable length code decoding circuit comprising: a shift register storing a bit sequence of variable bit length code variable of number of bits; decoding table storage means for storing data including an upper field selectively indicative of a meaning of the code and an address for next access, selected depending upon a state transition upon decoding said variable bit length code per n bits which n is an integer greater than or equal to two, an intermediate field indicative of a shifting magnitude of said shift register upon completion of decoding, and a lower field indicative of a state of code decoding; shift control means for shifting said bit sequence of said variable bit length code in said shift register for a shifting magnitude indicated in the intermediate field of data read out from said decoding table storage means; an initial data register storing an initial data having the same structure to data stored in said decoding table storage means and outputting said initial data every time of completion of decoding for one code; means for designating leading m bits of said shift register, which m is an integer smaller than or equal to n, depending upon the value in said intermediate field of one of said initial data and the data read out from said decoding table storage means; and means for generating an address for accessing said decoding table storage means by replacing the lower side of said initial data of said initial data register with the leading m bits of said shift register designated by said designating means upon initiation of decoding and by replacing the lower side of the upper field of data read out from said decoding table storage means with leading m bits of said shift register.

Claim 11

A variable length code decoding circuit comprising: a shift register storing a bit sequence of variable bit length code variable of number of bits; decoding table storage means for storing data including an upper field selectively indicative of a meaning of the code and an address for next access, selected depending upon a state transition upon decoding said variable bit length code per n bits which n is an integer greater than or equal to two, an intermediate field indicative of a shifting magnitude of said shift register upon completion of decoding, and a lower field indicative of a state of code decoding; shift control means for shifting said bit sequence of said variable bit length code in said shift register for a shifting magnitude indicated in the intermediate field of data read out from said decoding table storage means; an initial data register storing an initial data having the same structure to data stored in said decoding table storage means and outputting said initial data every time of completion of decoding for one code; means for designating leading m bits of said shift register, which m is an integer smaller than or equal to n, depending upon the value in said intermediate field of one of said initial data and the data read out from said decoding table storage means; and means for generating an address for accessing said decoding table storage means by replacing the lower side of said initial data of said initial data register with the leading m bits of said shift register designated by said designating means upon initiation of decoding and by replacing the lower side of the upper field of data read out from said decoding table storage means with leading m bits of said shift register.

Claim 12

A variable length code decoding circuit as set forth in claim 8, which further comprises an end data register for storing the content of said upper field of the read out data as a result of decoding when the data indicative of the code decoding state in the lower field of the data read out from said decoding table storage means indicates completion of decoding.

Claim 13

A variable length code decoding circuit comprising: a shift register storing a bit sequence of variable bit length code variable of number of bits; decoding table storage means for storing data including an upper field selectively indicative of a meaning of the code and an address for next access, selected depending upon a state transition upon decoding said variable bit length code per n bits which n is an integer greater than or equal to two, an intermediate field indicative of a shifting magnitude of said shift register upon completion of decoding, and a lower field indicative of a state of code decoding; shift control means for shifting said bit sequence of said variable bit length code in said shift register for a shifting magnitude indicated in the intermediate field of data read out from said decoding table storage means; leftmost one detecting means for searching leading k bits, which k is a positive integer, of said shift register and detecting a bit position where a bit containing "1" appears at first among said k bits; shift control means for shifting said bit sequence of said variable bit length code in said shift register for one of shifting magnitude indicated in the intermediate field of data read out from said decoding table storage means and shifting magnitude corresponding to the detected value of said leftmost one detecting means; an initial data register storing an initial data having the same structure to data stored in said decoding table storage means and outputting said initial data every time of completion of decoding for one code; means for designating leading m bits of said shift register, which m is an integer smaller than or equal to n, depending upon the value in said intermediate field of one of said initial data and the data read out from said decoding table storage means; adding means for adding said detected value of said leftmost one detecting means to said initial data of said initial data register; and means for generating an address for accessing said decoding table storage means with said added value of said adding means upon initiation of decoding and by replacing the lower side of the upper field of data read out from said decoding table storage means with leading m bits of said shift register.

Claim 14

A variable length code decoding circuit comprising: a shift register storing a bit sequence of variable bit length code variable of number of bits; decoding table storage means for storing data including an upper field selectively indicative of a meaning of the code and an address for next access, selected depending upon a state transition upon decoding said variable bit length code per n bits which n is an integer greater than or equal to two, an intermediate field indicative of a shifting magnitude of said shift register upon completion of decoding, and a lower field indicative of a state of code decoding; shift control means for shifting said bit sequence of said variable bit length code in said shift register for a shifting magnitude indicated in the intermediate field of data read out from said decoding table storage means; leftmost one detecting means for searching leading k bits, which k is a positive integer, of said shift register and detecting a bit position where a bit containing "1" appears at first among said k bits; shift control means for shifting said bit sequence of said variable bit length code in said shift register for one of shifting magnitude indicated in the intermediate field of data read out from said decoding table storage means and shifting magnitude corresponding to the detected value of said leftmost one detecting means; an initial data register storing an initial data having the same structure to data stored in said decoding table storage means and outputting said initial data every time of completion of decoding for one code; means for designating leading m bits of said shift register, which m is an integer smaller than or equal to n, depending upon the value in said intermediate field of one of said initial data and the data read out from said decoding table storage means; adding means for adding said detected value of said leftmost one detecting means to said initial data of said initial data register; and means for generating an address for accessing said decoding table storage means with said added value of said adding means upon initiation of decoding and by replacing the lower side of the upper field of data read out from said decoding table storage means with leading m bits of said shift register.

Claim 15

A variable length code decoding circuit as set forth in claim 10, which further comprises an end data register for storing the content of said upper field of the read out data as a result of decoding when the data indicative of the code decoding state in the lower field of the data read out from said decoding table storage means indicates completion of decoding.

Claim 16

A variable length code decoding circuit comprising: a shift register storing a bit sequence of variable bit length code variable of number of bits; decoding table storage means for storing data including an upper field selectively indicative of a meaning of the code and an address for next access, selected depending upon a state transition upon decoding said variable bit length code per n bits which n is an integer greater than or equal to two, an intermediate field indicative of a shifting magnitude of said shift register upon completion of decoding, and a lower field indicative of a state of code decoding; an initial data register storing an initial data having the same structure to data stored in said decoding table storage means and outputting said initial data every time of completion of decoding for one code; leftmost one detecting means for searching leading k bits, which k is a positive integer, of said shift register and detecting a bit position where a bit containing "1" appears at first among said k bits; shift control means for shifting said bit sequence of said variable bit length code in said shift register for one of shifting magnitude indicated in the intermediate field of data read out from said decoding table storage means and shifting magnitude corresponding to the detected value of said leftmost one detecting means; means for designating leading m bits of said shift register, which m is an integer smaller than or equal to n, depending upon the value in said intermediate field of one of said initial data and the data read out from said decoding table storage means; and means for generating an address for accessing said decoding table storage means by replacing lower side of said initial data with the detected value of said leftmost one detecting means upon initiation of decoding and by replacing the lower side of the upper field of data read out from said decoding table storage means with leading m bits of said shift register.

Claim 17

A variable length code decoding circuit comprising: a shift register storing a bit sequence of variable bit length code variable of number of bits; decoding table storage means for storing data including an upper field selectively indicative of a meaning of the code and an address for next access, selected depending upon a state transition upon decoding said variable bit length code per n bits which n is an integer greater than or equal to two, an intermediate field indicative of a shifting magnitude of said shift register upon completion of decoding, and a lower field indicative of a state of code decoding; an initial data register storing an initial data having the same structure to data stored in said decoding table storage means and outputting said initial data every time of completion of decoding for one code; leftmost one detecting means for searching leading k bits, which k is a positive integer, of said shift register and detecting a bit position where a bit containing "1" appears at first among said k bits; shift control means for shifting said bit sequence of said variable bit length code in said shift register for one of shifting magnitude indicated in the intermediate field of data read out from said decoding table storage means and shifting magnitude corresponding to the detected value of said leftmost one detecting means; means for designating leading m bits of said shift register, which m is an integer smaller than or equal to n, depending upon the value in said intermediate field of one of said initial data and the data read out from said decoding table storage means; and means for generating an address for accessing said decoding table storage means by replacing lower side of said initial data with the detected value of said leftmost one detecting means upon initiation of decoding and by replacing the lower side of the upper field of data read out from said decoding table storage means with leading m bits of said shift register.

Claim 18

A variable length code decoding circuit as set forth in claim 12, which further comprises an end data register for storing the content of said upper field of the read out data as a result of decoding when the data indicative of the code decoding state in the lower field of the data read out from said decoding table storage means indicates completion of decoding.