US5399890A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level
Assignee: Panasonic Holdings Corp
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Filing: 1994-06-10
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Granted: 1995-03-21
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Expires: 2014-06-10
Abstract
Abstract A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.
Inventors
- 👤 Shozo Okada
- 👤 Hisashi Ogawa
- 👤 Naoto Matsuo
- 👤 Yoshiro Nakata
- 👤 Toshiki Yabu
- 👤 Susumu Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:07
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/01; H10B12/02; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
203 words
A semiconductor memory comprising a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of said plurality of transistors to form a memory cell area, a plurality of first level interconnection layers connected to other portions of said plurality of transistors to form a peripheral circuit area, and a plurality of second level interconnection layers disposed above said stacked capacitors and said first level interconnection layers, wherein each of said plurality of stacked capacitors comprises a first electrode layer, a capacitance insulating film formed on top of said first electrode layer, and a second electrode layer formed on top of said capacitance insulating film, said second electrode layer being connected to a portion of one of said plurality of second level interconnection layers, at least portions of said plurality of first level interconnection layers are connected to other portions of said plurality of second level interconnection layers, and each of said plurality of first level interconnection layers shares the same layer as at least one of said first electrode layer and said second electrode layer, and said first level interconnection layers serve to interconnect said other portions of said plurality of transistors in said peripheral circuit area.
Claim 2
Dependent Claim
203 words
A semiconductor memory comprising a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of said plurality of transistors to form a memory cell area, a plurality of first level interconnection layers connected to other portions of said plurality of transistors to form a peripheral circuit area, and a plurality of second level interconnection layers disposed above said stacked capacitors and said first level interconnection layers, wherein each of said plurality of stacked capacitors comprises a first electrode layer, a capacitance insulating film formed on top of said first electrode layer, and a second electrode layer formed on top of said capacitance insulating film, said second electrode layer being connected to a portion of one of said plurality of second level interconnection layers, at least portions of said plurality of first level interconnection layers are connected to other portions of said plurality of second level interconnection layers, and each of said plurality of first level interconnection layers shares the same layer as at least one of said first electrode layer and said second electrode layer, and said first level interconnection layers serve to interconnect said other portions of said plurality of transistors in said peripheral circuit area.
Claim 3
Dependent Claim
28 words
A semiconductor memory according to claim 1, wherein each of said first level interconnection layers is formed from the same layer as that forming said first electrode layer.
Claim 4
Dependent Claim
28 words
A semiconductor memory according to claim 1, wherein each of said first level interconnection layers is formed from the same layer as that forming said second electrode layer.
Claim 5
Dependent Claim
215 words
A semiconductor memory comprising a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of said plurality of transistors, a plurality of first level interconnection layers connected to other portions of said plurality of transistors, and a plurality of second level interconnection layers disposed above said stacked capacitors and said first level interconnection layers. each of said plurality of stacked capacitors comprising a first electrode layer, a capacitance insulating film formed on top of said first electrode layer, and a second electrode layer formed on top of said capacitance insulating film, said second electrode layer being connected to a portion of one of said plurality of second level interconnection layers. at least portions of said plurality of first level interconnection layers being connected to other portions of said plurality of second level interconnection layers. each of said plurality of first level interconnection layers sharing the same layer as at least one of said first electrode layer and said second electrode layer, and wherein each of said first level interconnection layers comprises a lower layer section formed from the same layer as that forming said first electrode layer, and an upper layer section formed over said lower layer section from the same layer as that forming said second electrode layer.
Claim 6
Dependent Claim
215 words
A semiconductor memory comprising a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of said plurality of transistors, a plurality of first level interconnection layers connected to other portions of said plurality of transistors, and a plurality of second level interconnection layers disposed above said stacked capacitors and said first level interconnection layers. each of said plurality of stacked capacitors comprising a first electrode layer, a capacitance insulating film formed on top of said first electrode layer, and a second electrode layer formed on top of said capacitance insulating film, said second electrode layer being connected to a portion of one of said plurality of second level interconnection layers. at least portions of said plurality of first level interconnection layers being connected to other portions of said plurality of second level interconnection layers. each of said plurality of first level interconnection layers sharing the same layer as at least one of said first electrode layer and said second electrode layer, and wherein each of said first level interconnection layers comprises a lower layer section formed from the same layer as that forming said first electrode layer, and an upper layer section formed over said lower layer section from the same layer as that forming said second electrode layer.
Claim 7
Dependent Claim
22 words
A semiconductor memory according to claim 1, wherein each of said first level interconnection layers is formed from at least two layers.
Claim 8
Dependent Claim
20 words
A semiconductor memory according to claim 5, wherein each of said first level interconnection layers is formed from three layers.
Claim 9
Dependent Claim
38 words
A semiconductor memory according to claim 1, wherein each of said first level interconnection layers is formed from a single layer of a material chemically not easily reactive with said capacitance insulating film nor with said semiconductor substrate.
Claim 10
Dependent Claim
18 words
A semiconductor memory according to claim 7, wherein said capacitance insulating film is formed from a ferroelectric material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-20 | 1998-09-19 | 1999-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-20 | 2002-09-19 | 2003-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-20 | 2006-09-19 | 2007-03-21 | $7700.00 | Window Closed / Lapsed |