Semiconductor device with function of testing insulation defect between bit lines and testing method therefor

Claim 2

A semiconductor device comprising: a semiconductor substrate having a major surface; a function circuit formed in said substrate and having a preset function; a group of wiring layers connected to said function circuit and arranged in parallel to one another; a testing circuit formed in said substrate; first potential supplying means contained in said testing circuit and connected to even-numbered wiring layers in said wiring layer group, for supplying a first potential to said even-numbered wiring layers; and second potential supplying means contained in said testing circuit and connected to odd-numbered wiring layers in said wiring layer group, for supplying a second potential having a potential level different from the potential level of the first potential to said odd-numbered wiring layers.

Claim 3

The semiconductor device according to claim 1, wherein the potential level of the first potential is a positive level and the potential level of the second potential is a ground potential level.

Claim 4

The semiconductor device according to claim 1, wherein said function circuit is a memory matrix constructed by a plurality of memory cells and said wiring layer group is a bit line group.

Claim 5

The semiconductor device according to claim 1, wherein said second potential supplying means supplies the second potential to said odd-numbered wiring layers when said first potential supplying means supplies the first potential to said even-numbered wiring layers.

Claim 6

The semiconductor device according to claim 4, wherein an electrical stress is caused between said wiring layers by supplying said first potential to said even-numbered wiring layers and supplying said second potential to said odd-numbered wiring layers.

Claim 7

The semiconductor device according to claim 5, wherein the insulation property of a portion between said wiring layers is tested by causing an electrical stress between said wiring layers.

Claim 8

A semiconductor device comprising: a memory cell matrix having a plurality of memory cells arranged in a matrix form; a group of bit lines connected to said memory cells and provided for respective columns of said memory cell array; a testing circuit for effecting the test to check whether said memory cell matrix correctly functions or not; first potential supplying means contained in said testing circuit and having input and output terminals, said input terminal being supplied with a signal for commanding the start of the test and said output terminal being connected to even-numbered bit lines in said bit line group, for supplying a first potential to said even-numbered bit lines according to said signal; and second potential supplying means contained in said testing circuit and having input and output terminals, said input terminal being supplied with said signal and said output terminal being connected to odd-numbered bit lines in said bit line group, for supplying a second potential having a potential level different from the potential level of the first potential to said odd-numbered bit lines according to said signal.

Claim 9

A semiconductor device comprising: a memory cell matrix having a plurality of memory cells arranged in a matrix form; a group of bit lines connected to said memory cells and provided for respective columns of said memory cell array; a testing circuit for effecting the test to check whether said memory cell matrix correctly functions or not; first potential supplying means contained in said testing circuit and having input and output terminals, said input terminal being supplied with a signal for commanding the start of the test and said output terminal being connected to even-numbered bit lines in said bit line group, for supplying a first potential to said even-numbered bit lines according to said signal; and second potential supplying means contained in said testing circuit and having input and output terminals, said input terminal being supplied with said signal and said output terminal being connected to odd-numbered bit lines in said bit line group, for supplying a second potential having a potential level different from the potential level of the first potential to said odd-numbered bit lines according to said signal.

Claim 10

The semiconductor device according to claim 7, wherein the signal level of said signal supplied to said input terminal of said second potential supplying means is set to "0" when the signal level of said signal supplied to said input terminal of said first potential supplying means is set to "1" and the signal level of said signal supplied to said input terminal of said second potential supplying means is set to "1" when the signal level of said signal supplied to said input terminal of said first potential supplying means is set to "0".

Claim 11

The semiconductor device according to claim 7, wherein the potential level of said first potential is a positive level and the potential level of said second potential is a ground potential level.

Claim 12

The semiconductor device according to claim 7, wherein said second potential supplying means supplies the second potential to said odd-numbered bit lines when said first potential supplying means supplies the first potential to said even-numbered bit lines.

Claim 13

The semiconductor device according to claim 10, wherein an electrical stress is caused between said bit lines by supplying said first potential to said even-numbered bit lines and supplying said second potential to said odd-numbered bit lines.

Claim 14

The semiconductor device according to claim 11, wherein the insulation property of a portion between said wiring layers is tested by causing an electrical stress between said wiring layers.

Claim 15

A testing method for semiconductor devices, comprising the steps of: supplying a first potential to even-numbered bit lines among bit lines constructing a bit line group; supplying a second potential having a potential level different from the potential level of said first potential to odd-numbered bit lines among said bit lines constructing said bit line group with said first potential kept supplied to said even-numbered bit lines; and causing an electrical stress between bit lines by supplying said first potential to said even-numbered bit lines and supplying said second potential to said odd-numbered bit lines.

Claim 16

A testing method for semiconductor devices, comprising the steps of: supplying a first potential to even-numbered bit lines among bit lines constructing a bit line group; supplying a second potential having a potential level different from the potential level of said first potential to odd-numbered bit lines among said bit lines constructing said bit line group with said first potential kept supplied to said even-numbered bit lines; and causing an electrical stress between bit lines by supplying said first potential to said even-numbered bit lines and supplying said second potential to said odd-numbered bit lines.

Claim 17

The testing method for semiconductor devices, according to claim 13, wherein said electrical stress is caused to effect the test for insulation property in a portion between said bit lines.

Claim 18

The testing method for semiconductor devices, according to claim 14, further comprising the steps of: supplying a third potential having the same potential level as said first potential to odd-numbered bit lines among said bit lines constructing said bit line group with said first potential kept supplied to said even-numbered bit lines; and causing an electrical stress in said memory cells by supplying said first potential to said even-numbered bit lines and supplying said third potential to said odd-numbered bit lines.

Claim 19

The testing method for semiconductor devices, according to claim 15, wherein said electrical stress is caused to effect the test for the charge holding characteristics of said memory cells.

Claim 20

The testing method for semiconductor devices, according to claim 13, wherein said step of causing said electrical stress between said bit lines is effected after the packaging process.

Claim 21

The testing method for semiconductor devices, according to claim 15, wherein said step of causing said electrical stress between said bit lines and said step of causing said electrical stress in said memory cells are effected after the packaging process.

Claim 22

A semiconductor device comprising: first supplying means for supplying a first potential to even-numbered bit lines among bit lines constructing a bit line group; second potential supplying means for supplying a second potential having a potential level different from the potential level of said first potential to odd-numbered wiring layers among said bit lines constructing said bit line group; and a testing circuit containing said first and second supplying means, for causing an electrical stress between said bit lines by causing said first potential to be supplied to said even-numbered bit lines and causing said second potential to be supplied to said odd-numbered bit lines.

Claim 23

A semiconductor device comprising: first supplying means for supplying a first potential to even-numbered bit lines among bit lines constructing a bit line group; second potential supplying means for supplying a second potential having a potential level different from the potential level of said first potential to odd-numbered wiring layers among said bit lines constructing said bit line group; and a testing circuit containing said first and second supplying means, for causing an electrical stress between said bit lines by causing said first potential to be supplied to said even-numbered bit lines and causing said second potential to be supplied to said odd-numbered bit lines.

Claim 24

The semiconductor device according to claim 19, further comprising: third supplying means for supplying a third potential having the same potential level as said first potential to said odd-numbered bit lines among said bit lines constructing said bit line group with said first potential kept supplied to said even-numbered bit lines.

Claim 25

The semiconductor device according to claim 19, wherein said testing circuit contains said first, second and third supplying means, effects a first test mode for causing an electrical stress between said bit lines by causing said first potential to be supplied to said even-numbered bit lines and causing said second potential to be supplied to said odd-numbered bit lines, and effects a second test mode for causing an electrical stress in said memory cells by causing said first potential to be supplied to said even-numbered bit lines and causing said third potential to be supplied to said odd-numbered bit lines.