Peripheral port with volatile and non-volatile configuration

Claim 2

An integrated circuit including a peripheral port, the peripheral port comprising: an input/output pin; a multiplexer coupled to the input/output pin; a structure for providing one or more volatile configuration bits; and a structure for providing one or more non-volatile configuration bits, wherein the volatile configuration bits and the non-volatile configuration bits are asserted to select terminals of the multiplexer and control routing of signals through the multiplexer from or to the input/output pin, and one or more of the non-volatile configuration bits overrides one or more of the volatile configuration bits.

Claim 3

The integrated circuit of claim 1 wherein: when the non-volatile configuration bits have a first value, the volatile configuration bits control routing of signals through the multiplexer; and when the non-volatile configuration bits have a second value, the volatile configuration bits have no effect on the multiplexer.

Claim 4

The integrated circuit of claim 2, further comprising: a memory; and a data line connecting the memory to the multiplexer, wherein, when the non-volatile configuration bits have the second value, the non-volatile configuration bits control the multiplexer by causing the multiplexer to route a signal between the memory and the input/output pin.

Claim 5

The integrated circuit of claim 2, further comprising: a programmable array logic unit; and a macrocell connecting to the programmable array logic and to the multiplexer, wherein when the non-volatile configuration bits have the second value, the non-volatile configuration bits control the multiplexer by causing the multiplexer to route a signal between the macrocell and the input/output pin.

Claim 6

An integrated circuit including a peripheral port, comprising: an input/output pin; a multiplexer coupled to the input/output pin; a structure for providing one or more volatile configuration bits; a structure for providing one or more non-volatile configuration bits, wherein the volatile configuration bits and the non-volatile configuration bits control the multiplexer and one or more of the non-volatile configuration bits overrides one or more of the volatile configuration bits; a functional unit connected to the multiplexer and to the structure for providing non-volatile configuration bits, the structure for providing non-volatile configuration bits providing a particular non-volatile configuration bit which is usable to control operation of the functional unit; and a circuit which detects when the particular non-volatile configuration bit is used to control operation of the functional unit and which provides the particular non-volatile configuration bit for control of the multiplexer when the particular non-volatile configuration bit is not used to control the operation of the functional unit.

Claim 7

An integrated circuit including a peripheral port, comprising: an input/output pin; a multiplexer coupled to the input/output pin; a structure for providing one or more volatile configuration bits; a structure for providing one or more non-volatile configuration bits, wherein the volatile configuration bits and the non-volatile configuration bits control the multiplexer and one or more of the non-volatile configuration bits overrides one or more of the volatile configuration bits; a functional unit connected to the multiplexer and to the structure for providing non-volatile configuration bits, the structure for providing non-volatile configuration bits providing a particular non-volatile configuration bit which is usable to control operation of the functional unit; and a circuit which detects when the particular non-volatile configuration bit is used to control operation of the functional unit and which provides the particular non-volatile configuration bit for control of the multiplexer when the particular non-volatile configuration bit is not used to control the operation of the functional unit.

Claim 8

The integrated circuit of claim 5, wherein: the functional unit includes a programmable array logic unit and a macrocell, the macrocell being connected to the multiplexer; and the particular non-volatile bit is used to control the operation of the macrocell when the macrocell is used, and is usable to control the multiplexer when the macrocell is not used.

Claim 9

The integrated circuit of claim 1, wherein: the peripheral port further comprises a second multiplexer coupled to the input/output pin; the first multiplexer routes output signals to the input/output pin; and the second multiplexer routes input signals from the input/output pin.

Claim 10

The integrated circuit of claim 7, wherein the volatile configuration bits and the non-volatile configuration bits control routing of signals through the second multiplexer.

Claim 11

The integrated circuit of claim 7, wherein the volatile configuration bits and the non-volatile configuration bits that control the first multiplexer also control the second multiplexer.

Claim 12

An integrated circuit including a peripheral port, comprising: an input/output pin; a multiplexer coupled to the input/output pin; a structure for providing one or more volatile configuration bits; a structure for providing one or more non-volatile configuration bits; a first plurality of functional units, each functional unit in the first plurality of functional units being coupled to the multiplexer; and a second plurality of functional units, each of the functional units in the second plurality of functional units being connected to the multiplexer; wherein the volatile configuration bits and the non-volatile configuration bits control the multiplexer and one or more of the non-volatile configuration bits overrides one or more of the volatile configuration bits such that: when the non-volatile configuration bits have a first value, the volatile configuration bits control the multiplexer by causing the multiplexer to route a signal between the input/output pin and a selected functional unit in the first plurality of functional units; and when the non-volatile configuration bits have a value other than the first value, the volatile configuration bits have no effect on the multiplexer and the non-volatile configuration bits control the multiplexer by causing the multiplexer to route a signal between the input/output pin and a functional unit in the second plurality of functional units.

Claim 13

An integrated circuit including a peripheral port, comprising: an input/output pin; a multiplexer coupled to the input/output pin; a structure for providing one or more volatile configuration bits; a structure for providing one or more non-volatile configuration bits; a first plurality of functional units, each functional unit in the first plurality of functional units being coupled to the multiplexer; and a second plurality of functional units, each of the functional units in the second plurality of functional units being connected to the multiplexer; wherein the volatile configuration bits and the non-volatile configuration bits control the multiplexer and one or more of the non-volatile configuration bits overrides one or more of the volatile configuration bits such that: when the non-volatile configuration bits have a first value, the volatile configuration bits control the multiplexer by causing the multiplexer to route a signal between the input/output pin and a selected functional unit in the first plurality of functional units; and when the non-volatile configuration bits have a value other than the first value, the volatile configuration bits have no effect on the multiplexer and the non-volatile configuration bits control the multiplexer by causing the multiplexer to route a signal between the input/output pin and a functional unit in the second plurality of functional units.