US5402386A
Expired / Lapsed
US
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Word line decoder/driver circuit and method
Assignee: Sun Microsystems Inc
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Filing: 1993-07-15
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Granted: 1995-03-28
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Expires: 2013-07-15
Abstract
Abstract A row select circuit for semiconductor memories is disclosed. The row select circuit includes a decoder portion and a driver portion. The decoder potion of the row select circuit includes a plurality of decoder circuits, each servicing a multiplicity of rows. Two levels of decoding are used to select a row. First, one of the plurality of decoder circuits is selected. Second, a predecoder is provided for simultaneously selecting one of the multiplicity of rows serviced by the selected decoder circuit. A single current source is used to service the multiplicity of rows associated with a particular decoder. The driver portion of the circuit includes a driver circuit for each row. Each driver includes an inverter stage, a driver stage, a clamp and a voltage reference circuit. For a selected row, the driver circuit provides ultra-fast access time. For the deselected rows, the driver circuit consumes minimal power.
Inventors
- 👤 Lee S. Tavrow
- 👤 Mark R. Santoro
- 👤 Gary W. Bewick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 03:10
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/18
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
65 words
A semiconductor memory circuit, comprising: a multiplicity of rows; a row decoder circuit for selecting one of the multiplicity of rows; and a differential pair including a current source, a first transistor and a second transistor, coupled between the row decoder and the multiplicity of rows, the differential pair for providing current from the current source to the selected one of the multiplicity of rows.
Claim 2
Dependent Claim
65 words
A semiconductor memory circuit, comprising: a multiplicity of rows; a row decoder circuit for selecting one of the multiplicity of rows; and a differential pair including a current source, a first transistor and a second transistor, coupled between the row decoder and the multiplicity of rows, the differential pair for providing current from the current source to the selected one of the multiplicity of rows.
Claim 3
Dependent Claim
33 words
The circuit of claim 1, wherein in the event one of the multiplicity of rows is selected, current from the constant current source is switched from the current source to the selected row.
Claim 4
Dependent Claim
23 words
The circuit of claim 1, wherein the row decoder includes a decoder logic circuit coupled to the second transistor of the differential pair.
Claim 5
Dependent Claim
38 words
The circuit of claim 3, wherein a voltage reference is coupled to a control electrode of the first transistor and the decoder logic circuit is coupled to a control electrode of the second transistor of the differential pair.
Claim 6
Dependent Claim
23 words
The circuit of claim 1, wherein each of the multiplicity of rows further comprises a row select node and a pull up resistor.
Claim 7
Dependent Claim
18 words
The circuit of claim 5, wherein each of the multiplicity of rows further comprises a row select transistor.
Claim 8
Dependent Claim
45 words
The circuit of claim 6, wherein in the event a row in the decoder circuit is selected, current from the current source is switched through the row select transistor and the pull up resistor, thereby pulling down the row select node for the selected row.
Claim 9
Dependent Claim
24 words
The circuit of claim 7, wherein each of the multiplicity of rows includes an inverter and a driver circuit coupled to the switching node.
Claim 10
Dependent Claim
17 words
The circuit of claim 1, further comprising a predecoder for selecting one of the multiplicity of rows.
Claim 11
Dependent Claim
35 words
The circuit of claim 2, wherein in the event the decoder circuit is deselected, a current path is established between the current source and the second transistor of the differential pair to a power source.
Claim 12
Dependent Claim
74 words
A driver circuit on a semiconductor memory, comprising: an input node coupled to receive a row select signal, a driver stage for amplifying the row select signal; a switching clamp, coupled to the driver stage, for reducing the effects of overshoot in the driver stage; an output node for outputting the amplified row select signal; and a row coupled to the output node and being selected in response to the amplified row select signal.
Claim 13
Dependent Claim
74 words
A driver circuit on a semiconductor memory, comprising: an input node coupled to receive a row select signal, a driver stage for amplifying the row select signal; a switching clamp, coupled to the driver stage, for reducing the effects of overshoot in the driver stage; an output node for outputting the amplified row select signal; and a row coupled to the output node and being selected in response to the amplified row select signal.
Claim 14
Dependent Claim
29 words
The circuit of claim 11, wherein the amplifier stage comprises a plurality of transistors arranged in a cascaded emitter-follower configuration for amplifying the current of the row select signal.
Claim 15
Dependent Claim
14 words
The circuit of claim 11, wherein the amplifier stage comprises three cascaded emitter-follower transistors.
Claim 16
Dependent Claim
40 words
The circuit of claim 11, wherein the switching clamp is switched on when a predetermined voltage at the amplifier stage is exceeded, thereby minimizing the effect of overshoot in the amplifier stage by shunting current away from the amplifier stage.
Claim 17
Dependent Claim
15 words
The circuit of claim 11, wherein current gain of the amplifier stage is selectively controlled.
Claim 18
Dependent Claim
33 words
The circuit of claim 15, wherein the gain of the amplifier stage is selectively controlled by varying the effective emitter size of a transistor and a diode respectively associated with the amplifier stage.
Claim 19
Dependent Claim
15 words
The circuit of claim 16, wherein the gain of the amplifier stage is process independent.
Claim 20
Dependent Claim
27 words
The circuit of claim 11, wherein the amplifier stage includes a discharge path which acts as a current source during row drive operation of the amplifier stage.
Claim 21
Dependent Claim
27 words
The circuit of claim 18, wherein the current source of the discharge path is automatically shut off when the row associated with the driver stage is deselected.
Claim 22
Dependent Claim
33 words
The circuit of claim 11, further comprising an inverter stage, coupled to invert the row select signal and to provide the inverted row select signal to the input node of the driver stage.
Claim 23
Dependent Claim
34 words
The circuit of claim 20, wherein the inverter stage inverts and translates the row select signal operating in a first voltage range to the inverted row select signal operating in a second voltage range.
Claim 24
Dependent Claim
62 words
A circuit on a semiconductor memory, comprising: a translating stage for receiving a deselect signal at a first voltage and translating it to a second voltage; a row; a driver stage coupled between the translating stage and the row, wherein the driver stage has a voltage drop approximately equal to the second voltage and; a current mirror coupled to the driver stage.
Claim 25
Dependent Claim
62 words
A circuit on a semiconductor memory, comprising: a translating stage for receiving a deselect signal at a first voltage and translating it to a second voltage; a row; a driver stage coupled between the translating stage and the row, wherein the driver stage has a voltage drop approximately equal to the second voltage and; a current mirror coupled to the driver stage.
Claim 26
Dependent Claim
21 words
The circuit of claim 22, further comprising a voltage reference circuit coupled to the translating stage for establishing the second voltage.
Claim 27
Dependent Claim
20 words
The circuit of claim 22, wherein the current mirror includes a plurality of transistors arranged in a cascaded emitter-follower configuration.
Claim 28
Dependent Claim
20 words
The circuit of claim 22, wherein the driver stage includes a plurality of transistors arranged in a cascaded emitter-follower configuration.
Claim 29
Dependent Claim
14 words
The circuit of claim 22, wherein the voltage at the row is approximately zero.
Claim 30
Independent Claim
87 words
A method of driving a selected row in a memory array, comprising the steps of: receiving a signal at an input node of an amplifying stage; amplifying, in a series of cascaded amplifier stages, the row select signal; pulling up an output node, coupled to a selected row in a memory array, in response to the amplified row select signal; and in the event of voltage overshoot conditions in the cascaded amplifier stages, turning on a clamp to shunt excess current away from the cascaded amplifier stages.
Claim 31
Independent Claim
87 words
A method of driving a selected row in a memory array, comprising the steps of: receiving a signal at an input node of an amplifying stage; amplifying, in a series of cascaded amplifier stages, the row select signal; pulling up an output node, coupled to a selected row in a memory array, in response to the amplified row select signal; and in the event of voltage overshoot conditions in the cascaded amplifier stages, turning on a clamp to shunt excess current away from the cascaded amplifier stages.
Claim 32
Dependent Claim
28 words
The method of claim 27, further comprising the step of inverting the signal before the step of receiving the signal at the input node of the amplifier stage.
Claim 33
Dependent Claim
20 words
The method of claim 27, wherein the amplifying step includes the step of increasing the current gain of the signal.
Claim 34
Dependent Claim
29 words
The method of claim 27, wherein the amplifying step further comprises the step of amplifying the row select signal through a plurality of transistors arranged in an emitter-follower configuration.
Claim 35
Dependent Claim
21 words
The method of claim 27, further comprising the step of discharging the output node after the selected row has been selected.
Claim 36
Independent Claim
98 words
A method of reducing power consumption of a deselected row in a memory array, comprising the steps of: receiving a row deselect signal at a first predetermined voltage; translating the row deselect signal to a second predetermined voltage; applying the translated row select signal at the second predetermined voltage at an input node of a driver circuit having a voltage drop approximately equal to the second predetermined voltage; outputting the row deselect signal at an output node of the driver circuit and; providing a current mirror to substantially minimize any current from being dissipated at the output node.
Claim 37
Independent Claim
98 words
A method of reducing power consumption of a deselected row in a memory array, comprising the steps of: receiving a row deselect signal at a first predetermined voltage; translating the row deselect signal to a second predetermined voltage; applying the translated row select signal at the second predetermined voltage at an input node of a driver circuit having a voltage drop approximately equal to the second predetermined voltage; outputting the row deselect signal at an output node of the driver circuit and; providing a current mirror to substantially minimize any current from being dissipated at the output node.
Claim 38
Dependent Claim
17 words
The method of claim 32, wherein the first predetermined voltage is established by a reference voltage circuit.
Claim 39
Dependent Claim
122 words
A row driver circuit on a semiconductor memory, comprising: an input node for receiving either a row select or a row deselect signal; a translator for translating the row select signal or the row deselect signal; an amplifier stage for amplifying the translated row select signal, or reducing the potential of the row deselect signal for minimizing power dissipation of the amplifier stage in response to the row deselect signal; a clamp, coupled to the amplifier stage, for reducing the effect of overshoot in the amplifier stage in response to the row select signal; a row coupled to the output of the amplifier stage and selected in response to the row select signal or deselected in response to the row deselect signal.
Claim 40
Dependent Claim
122 words
A row driver circuit on a semiconductor memory, comprising: an input node for receiving either a row select or a row deselect signal; a translator for translating the row select signal or the row deselect signal; an amplifier stage for amplifying the translated row select signal, or reducing the potential of the row deselect signal for minimizing power dissipation of the amplifier stage in response to the row deselect signal; a clamp, coupled to the amplifier stage, for reducing the effect of overshoot in the amplifier stage in response to the row select signal; a row coupled to the output of the amplifier stage and selected in response to the row select signal or deselected in response to the row deselect signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-27 | 1998-09-26 | 1999-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-27 | 2002-09-26 | 2003-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-27 | 2006-09-26 | 2007-03-28 | $7700.00 | Window Closed / Lapsed |