US5406524A
Expired / Lapsed
US
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Nonvolatile semiconductor memory that eases the dielectric strength requirements
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1994-01-25
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Granted: 1995-04-11
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Expires: 2014-01-25
Abstract
Abstract An object of the present invention is to ease the dielectric strength requirements for transistors forming power supply circuits or the like. A nonvolatile semiconductor memory of the present invention includes a plurality of memory cells, each of which is composed of a floating gate, a control gate, a drain, and a source, and a negative voltage generating means whose generated negative voltage is applied to the control gate for drawing a charge stored in the floating gate into a channel or the source when stored data is erased electrically. The nonvolatile memory of the present invention further includes positive erasure voltage generating means, and a positive voltage higher than a conventional supply voltage generated by the positive erasure voltage generating means is applied to the channel or the source.
Inventors
- 👤 Shouichi Kawamura
- 👤 Nobuaki Takashina
- 👤 Yasushi Kasa
- 👤 Kiyoshi Itano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:52
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/06; G11C16/10; G11C16/14; G11C16/30; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
103 words
A nonvolatile semiconductor memory comprising: a plurality of memory cells, each of said memory cells including a floating gate, a control gate, a drain, and a source; a negative voltage generating means whose generated negative voltage is applied to said control gate for drawing a charge stored in said floating gate into a channel formed between said drain and said source in each memory cell when stored data is erased electrically; and positive erasure voltage generating means which generates a positive voltage higher than a supply voltage, said positive voltage generated by said positive erasure voltage generating means being applied to said channel.
Claim 2
Dependent Claim
103 words
A nonvolatile semiconductor memory comprising: a plurality of memory cells, each of said memory cells including a floating gate, a control gate, a drain, and a source; a negative voltage generating means whose generated negative voltage is applied to said control gate for drawing a charge stored in said floating gate into a channel formed between said drain and said source in each memory cell when stored data is erased electrically; and positive erasure voltage generating means which generates a positive voltage higher than a supply voltage, said positive voltage generated by said positive erasure voltage generating means being applied to said channel.
Claim 3
Dependent Claim
40 words
A nonvolatile semiconductor memory according to claim 1, wherein said positive voltage generated by said positive erasure voltage generating means is applied to said drain of each memory cell when a charge is injected into said floating gate for writing.
Claim 4
Dependent Claim
100 words
A nonvolatile semiconductor memory comprising: a plurality of memory cells, each of said memory cells including a floating gate, a control gate, a drain, and a source; a negative voltage generating means whose generated negative voltage is applied to said control gate for drawing a charge stored in said floating gate into said source of each memory cell when stored data is erased electrically; and positive erasure voltage generating means which generates a positive voltage higher than a supply voltage, said positive voltage generated by said positive erasure voltage generating means being applied to said source of each memory cell.
Claim 5
Dependent Claim
100 words
A nonvolatile semiconductor memory comprising: a plurality of memory cells, each of said memory cells including a floating gate, a control gate, a drain, and a source; a negative voltage generating means whose generated negative voltage is applied to said control gate for drawing a charge stored in said floating gate into said source of each memory cell when stored data is erased electrically; and positive erasure voltage generating means which generates a positive voltage higher than a supply voltage, said positive voltage generated by said positive erasure voltage generating means being applied to said source of each memory cell.
Claim 6
Dependent Claim
40 words
A nonvolatile semiconductor memory according to claim 3, wherein said positive voltage generated by said positive erasure voltage generating means is applied to said drain of each memory cell when a charge is injected into said floating gate for writing.
References Cited (Backward Citations)
US3660819A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-04-10 | 1998-10-10 | 1999-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-10 | 2002-10-10 | 2003-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-10 | 2006-10-10 | 2007-04-11 | $7700.00 | Window Closed / Lapsed |