Non-volatile memory cell

Claim 2

A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type having an upper portion; a pair of impurity diffusion regions of a second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the pair of impurity diffusion regions in the upper portion of the semiconductor layer; a gate insulating film provided on the upper portion of the semiconductor layer, having thin portions covering at least part of the pair of impurity diffusion regions and a thick portion covering the channel region; floating gate electrodes provided on the thin portions of the gate insulating film; a control gate electrode provided on the thick portion of the gate insulating film and electrically insulated from the floating gate electrodes; and an insulating film provided between the control gate electrode and the floating gate electrodes, capacity-coupling the control gate electrode with the floating gate electrodes, wherein, during writing data, part of electric carriers in the impurity diffusion regions are injected into the floating gate electrodes through the thin portions of the gate insulating film so as to form a Fowler-Nordheim current, depending upon a voltage to be applied to the control gate electrode, whereby electric resistance of the impurity diffusion regions is changed.

Claim 3

A non-volatile memory cell according to claim 1, wherein the thin portions have substantially the same thickness.

Claim 4

A non-volatile memory cell according to claim 1, wherein the thin portions have a thickness of approximately 5 nanometers or more.

Claim 5

A non-volatile memory cell according to claim 1, wherein the floating gate electrodes are connected to each other on an upper surface of the control gate electrode.

Claim 6

A non-volatile memory cell according to claim 1, wherein at least one of the thin portions has a multi-layered structure.

Claim 7

A non-volatile memory cell according to claim 5, wherein the multi-layered structure includes an oxide film and a silicon nitride film.

Claim 8

A non-volatile memory cell according to claim 1, wherein the thin portions have different thicknesses.

Claim 9

A non-volatile memory cell according to claim 7, wherein at least one of the thin portions has a multi-layered structure.

Claim 10

A non-volatile memory cell according to claim 7, wherein logic data corresponding to three different values can be stored in the memory cell.

Claim 11

A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type having an upper portion; a pair of impurity diffusion regions of a second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the pair of impurity diffusion regions in the upper portion of the semiconductor layer; a gate insulating film provided on the upper portion of the semiconductor layer, having thin portions covering at least part of the pair of impurity diffusion regions and a thick portion covering the channel region; at least one floating gate electrode provided on a respective one of the thin portions of the gate insulating film; a control gate electrode provided on the thick portion of the gate insulating film and electrically insulated from the at least one floating gate electrode; and an insulating film provided between the control gate electrode and the at least one floating gate electrode, capacity-coupling the control gate electrode with the at least one floating gate electrode, wherein, during writing data, part of electric carriers in the impurity diffusion regions are injected into the at least one floating gate electrodes through the respective one of the thin portions of the gate insulating film so as to form a Fowler-Nordheim current, depending upon a voltage to be applied to the control gate electrode, whereby electric resistance of the impurity diffusion region covered by the respective one of the thin portions of the gate insulating film is changed.

Claim 12

A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type having an upper portion; a pair of impurity diffusion regions of a second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the pair of impurity diffusion regions in the upper portion of the semiconductor layer; a gate insulating film provided on the upper portion of the semiconductor layer, having thin portions covering at least part of the pair of impurity diffusion regions and a thick portion covering the channel region; at least one floating gate electrode provided on a respective one of the thin portions of the gate insulating film; a control gate electrode provided on the thick portion of the gate insulating film and electrically insulated from the at least one floating gate electrode; and an insulating film provided between the control gate electrode and the at least one floating gate electrode, capacity-coupling the control gate electrode with the at least one floating gate electrode, wherein, during writing data, part of electric carriers in the impurity diffusion regions are injected into the at least one floating gate electrodes through the respective one of the thin portions of the gate insulating film so as to form a Fowler-Nordheim current, depending upon a voltage to be applied to the control gate electrode, whereby electric resistance of the impurity diffusion region covered by the respective one of the thin portions of the gate insulating film is changed.

Claim 13

A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type having an upper portion; a source region of a second conductivity type and a drain region of the second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the source region and the drain region in the upper portion of the semiconductor layer; a first gate insulating film provided on the upper portion of the semiconductor layer, having a first portion covering a part of the source region, a second portion covering a part of the drain region, and a third portion covering the channel region; an insulating film provided on the upper portion of the semiconductor layer, having a first portion covering another part of the source region and a second portion covering another part of the drain region; a first floating gate electrode provided on the first portion of the first gate insulating film; a second floating gate electrode provided on the second portion of the first gate insulating film; a third floating gate electrode provided on the first portion of the insulating film; a fourth floating gate electrode provided on the second portion of the insulating film; a first portion of a second gate insulating film providing between the first floating gate electrode and the third floating gate electrode; and a second portion of the second gate insulating film provided between the second floating gate electrode and the fourth floating gate electrode, wherein the first, second, third, and fourth floating gate electrodes are capacity-coupled with the control gate electrode, wherein, during writing data, part of electric carriers in the source region and/or the drain region are injected into the first floating gate electrode and/or the second floating gate electrode through the first portion and/or the second portion of the first gate insulating film and are injected into the third floating gate electrode and/or the fourth floating gate insulating film and/or the second portion of the second gate insulating film so as to form a Fowler-Nordheim current, depending upon a voltage to be applied to the control gate electrode.

Claim 14

A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type having an upper portion; a source region of a second conductivity type and a drain region of the second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the source region and the drain region in the upper portion of the semiconductor layer; a first gate insulating film provided on the upper portion of the semiconductor layer, having a first portion covering a part of the source region, a second portion covering a part of the drain region, and a third portion covering the channel region; an insulating film provided on the upper portion of the semiconductor layer, having a first portion covering another part of the source region and a second portion covering another part of the drain region; a first floating gate electrode provided on the first portion of the first gate insulating film; a second floating gate electrode provided on the second portion of the first gate insulating film; a third floating gate electrode provided on the first portion of the insulating film; a fourth floating gate electrode provided on the second portion of the insulating film; a first portion of a second gate insulating film providing between the first floating gate electrode and the third floating gate electrode; and a second portion of the second gate insulating film provided between the second floating gate electrode and the fourth floating gate electrode, wherein the first, second, third, and fourth floating gate electrodes are capacity-coupled with the control gate electrode, wherein, during writing data, part of electric carriers in the source region and/or the drain region are injected into the first floating gate electrode and/or the second floating gate electrode through the first portion and/or the second portion of the first gate insulating film and are injected into the third floating gate electrode and/or the fourth floating gate insulating film and/or the second portion of the second gate insulating film so as to form a Fowler-Nordheim current, depending upon a voltage to be applied to the control gate electrode.

Claim 15

A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type having an upper portion; a source region of a second conductivity type and a drain region of the second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the source region and the drain region in the upper portion of the semiconductor layer; a first gate insulating film providing on the upper portion of the semiconductor layer, having a first portion covering at least part of the source region, a second portion covering at least part of the drain region, and a third portion covering the channel region; a first floating gate electrode provided on the first portion of the first gate insulating film; a second floating gate electrode provided on the second portion of the first gate insulating film; a control gate electrode provided on the third portion of the first gate insulating film and electrically insulated from the first and second floating gate electrodes; a first insulating film provided between the control gate electrode and the first floating gate electrode, capacity-coupling the control gate electrode with the first floating gate electrode; and a second insulating film provided between the control gate electrode and the second floating gate electrode, capacity-coupling the control gate electrode with the second floating gate electrode, wherein a degree of capacitive coupling due to the first insulating film is different from a degree of capacitive coupling due to the second insulating film, wherein, during writing data, part of electric carriers in the source region and/or the drain region are injected into the first floating gate electrode and/or the second floating gate electrode through the first portion and/or the second portion of the first gate insulating film so as to form a Fowler-Nordheim current, depending upon a voltage to be applied to the control gate electrode.

Claim 16

A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type having an upper portion; a source region of a second conductivity type and a drain region of the second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the source region and the drain region in the upper portion of the semiconductor layer; a first gate insulating film providing on the upper portion of the semiconductor layer, having a first portion covering at least part of the source region, a second portion covering at least part of the drain region, and a third portion covering the channel region; a first floating gate electrode provided on the first portion of the first gate insulating film; a second floating gate electrode provided on the second portion of the first gate insulating film; a control gate electrode provided on the third portion of the first gate insulating film and electrically insulated from the first and second floating gate electrodes; a first insulating film provided between the control gate electrode and the first floating gate electrode, capacity-coupling the control gate electrode with the first floating gate electrode; and a second insulating film provided between the control gate electrode and the second floating gate electrode, capacity-coupling the control gate electrode with the second floating gate electrode, wherein a degree of capacitive coupling due to the first insulating film is different from a degree of capacitive coupling due to the second insulating film, wherein, during writing data, part of electric carriers in the source region and/or the drain region are injected into the first floating gate electrode and/or the second floating gate electrode through the first portion and/or the second portion of the first gate insulating film so as to form a Fowler-Nordheim current, depending upon a voltage to be applied to the control gate electrode.

Claim 17

A non-volatile memory cell according to claim 12, wherein a thickness of the first insulating film is different from a thickness of the second insulating film.

Claim 18

A non-volatile memory cell according to claim 12, wherein a dielectric constant of the first insulating film is different from a dielectric constant of the second insulating film.

Claim 19

A non-volatile memory cell according to claim 12, further comprising: a second gate insulating film provided so as to cover the first and second floating gate electrodes, having a first portion covering the first floating gate electrode and a second portion covering the second floating gate electrode; a third floating gate electrode provided on the first portion of the second gate insulating film; and a fourth floating gate electrode provided on the second portion of the second gate insulating film, wherein the third and fourth floating gate electrodes are capacity-coupled with the control gate electrode, wherein, during writing data, part of electric carriers in the source region and/or the drain region are injected into the first floating gate electrode and/or the second floating gate electrode through the first portion and/or the second portion of the first gate insulating film and are injected into the third floating gate electrode and/or the fourth floating gate electrode through the first portion and/or the second portion of the second gate insulating film so as to form a Fowler-Nordheim current, depending upon a voltage to be applied to the control gate electrode.

Claim 20

A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type having an upper portion; a source region of a second conductivity type and a drain region of the second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the source region and the drain region in the upper portion of the semiconductor layer; a first gate insulating film provided on the upper portion of the semiconductor layer, having a first portion covering at least part of the source region, a second portion covering at least part of the drain region, and a third portion covering the channel region; a first floating gate electrode provided on the first portion of the first gate insulating film; a second floating gate electrode provided on the second portion of the first gate insulating film; a control gate electrode provided on the third portion of the first gate insulating film and electrically insulated from the first and second floating gate electrodes; a second gate insulating film provided so as to cover the first and second floating gate electrodes, having a first portion covering the first floating gate electrode and a second portion covering the second floating gate electrode; a third floating gate electrode provided on the first portion of the second gate insulating film; and a fourth floating gate electrode provided on the second portion of the second gate insulating film, wherein the first, second, third, and fourth floating gate electrodes are capacity-coupled with the control gate electrode, wherein, during writing data, part of electric carriers in the source region and/or the drain region are injected into the first floating gate electrode and/or the second floating gate electrode through the first portion and/or the second portion of the first gate insulating film and are injected into the third floating gate electrode and/or the fourth floating gate electrode through the first portion and/or the second portion of the second gate insulating film so as to form a Fowler-Nordheim current, depending upon a voltage to be applied to the control gate electrode.

Claim 21

A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type having an upper portion; a source region of a second conductivity type and a drain region of the second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the source region and the drain region in the upper portion of the semiconductor layer; a first gate insulating film provided on the upper portion of the semiconductor layer, having a first portion covering at least part of the source region, a second portion covering at least part of the drain region, and a third portion covering the channel region; a first floating gate electrode provided on the first portion of the first gate insulating film; a second floating gate electrode provided on the second portion of the first gate insulating film; a control gate electrode provided on the third portion of the first gate insulating film and electrically insulated from the first and second floating gate electrodes; a second gate insulating film provided so as to cover the first and second floating gate electrodes, having a first portion covering the first floating gate electrode and a second portion covering the second floating gate electrode; a third floating gate electrode provided on the first portion of the second gate insulating film; and a fourth floating gate electrode provided on the second portion of the second gate insulating film, wherein the first, second, third, and fourth floating gate electrodes are capacity-coupled with the control gate electrode, wherein, during writing data, part of electric carriers in the source region and/or the drain region are injected into the first floating gate electrode and/or the second floating gate electrode through the first portion and/or the second portion of the first gate insulating film and are injected into the third floating gate electrode and/or the fourth floating gate electrode through the first portion and/or the second portion of the second gate insulating film so as to form a Fowler-Nordheim current, depending upon a voltage to be applied to the control gate electrode.

Claim 22

A non-volatile memory cell according to claim 16, wherein a thickness of the first portion of the second gate insulating film is equal to a thickness of the second portion of the second gate insulating film.

Claim 23

A non-volatile memory cell according to claim 16, wherein a thickness of the first portion of the first gate insulating film is equal to a thickness of the second portion of the first gate insulating film.

Claim 24

A non-volatile memory cell according to claim 18, wherein the control gate electrode completely covers the channel region.

Claim 25

A non-volatile memory cell according to claim 16, wherein the thickness of the first portion of the first gate insulating film is smaller than the thickness of the second portion of the first gate insulating film.

Claim 26

A non-volatile memory cell according to claim 20, wherein the thickness of the second portion of the second gate insulating film is smaller than the thickness of the first portion of the second gate insulating film.

Claim 27

A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type having an upper portion; a source region of a second conductivity type and a drain region of the second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the source region and the drain region in the upper portion of the semiconductor layer; a first gate insulating film provided on the upper portion of the semiconductor layer, having a first portion covering one part of the source region, a second portion covering one part of the drain region, and a third portion covering the channel region; a second gate insulating film provided on the upper portion of the semiconductor layer, having a first portion covering another part of the source region, and a second portion covering another part of the drain region; a first floating gate electrode provided on the first portion of the first gate insulating film; a second floating gate electrode provided on the second portion of the first gate insulating film; a control gate electrode provided on the third portion of the first gate insulating film and electrically insulating from the first and second floating gate electrodes; a third floating gate electrode provided on the first portion of the second gate insulating film; and a fourth floating gate electrode provided on the second portion of the second gate insulating film, wherein the first, second, third, and fourth floating gate electrodes are capacity-coupled with the control gate electrode, wherein, during writing date, part of electric carriers in the source region and/or the drain region are injected into the first floating gate electrode and/or the second floating gate electrode through the first portion and/or the second portion of the first gate insulating film and are injected into the third floating gate electrode and/or the fourth floating gate electrode through the first portion and/or the second portion of the second gate insulating film so as to form a Fowler-Nordheim current, depending upon a voltage to be applied to the control gate electrode.

Claim 28

A non-volatile memory cell comprising: a semiconductor layer of a first conductivity type having an upper portion; a source region of a second conductivity type and a drain region of the second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the source region and the drain region in the upper portion of the semiconductor layer; a first gate insulating film provided on the upper portion of the semiconductor layer, having a first portion covering one part of the source region, a second portion covering one part of the drain region, and a third portion covering the channel region; a second gate insulating film provided on the upper portion of the semiconductor layer, having a first portion covering another part of the source region, and a second portion covering another part of the drain region; a first floating gate electrode provided on the first portion of the first gate insulating film; a second floating gate electrode provided on the second portion of the first gate insulating film; a control gate electrode provided on the third portion of the first gate insulating film and electrically insulating from the first and second floating gate electrodes; a third floating gate electrode provided on the first portion of the second gate insulating film; and a fourth floating gate electrode provided on the second portion of the second gate insulating film, wherein the first, second, third, and fourth floating gate electrodes are capacity-coupled with the control gate electrode, wherein, during writing date, part of electric carriers in the source region and/or the drain region are injected into the first floating gate electrode and/or the second floating gate electrode through the first portion and/or the second portion of the first gate insulating film and are injected into the third floating gate electrode and/or the fourth floating gate electrode through the first portion and/or the second portion of the second gate insulating film so as to form a Fowler-Nordheim current, depending upon a voltage to be applied to the control gate electrode.

Claim 29

A non-volatile memory cell according to claim 22, wherein a thickness of the first portion of the first gate insulating film is equal to a thickness of the second portion of the first gate insulating film.

Claim 30

A non-volatile memory cell according to claim 22, wherein a thickness of the first portion of the second gate insulating film is equal to a thickness of the second portion of the second gate insulating film.

Claim 31

A non-volatile memory cell according to claim 22, wherein the control gate electrode completely covers the channel region.

Claim 32

A non-volatile memory cell according to claim 22, wherein the thickness of the first portion of the first gate insulating film is smaller than the thickness of the second portion of the first gate insulating film.

Claim 33

A non-volatile memory cell according to claim 26, wherein the thickness of the second portion of the second gate insulating film is smaller than the thickness of the first portion of the second gate insulating film.