Double precision division circuit and method for digital signal processor

Claim 2

A double precision division circuit, comprising: a data bus having a data path N bits wide; data registers that store first and second portions of a signed 4N bit dividend, a signed 2N bit divisor, and a signed 2N bit quotient; said dividend, divisor and quotient each including a sign bit; said first and second portions of said 4N bit dividend being stored as two 2N bit values in two distinct data registers; an arithmetic logic unit (ALU) coupled to said data registers for receiving from said data registers said first portion of said signed 4N bit dividend and said signed 2N bit divisor, for performing specified arithmetic operations to generate an output value having a sign bit and for replacing said first portion of said signed 4N bit dividend stored in said data registers with said output value; logic circuitry coupled to said ALU for generating an operation bit value QOP and a quotient bit QB in accordance with said sign bit of said signed 2N bit divisor and said sign bit of one of said output value and said signed 4N bit dividend; shift circuitry for receiving said signed 2N bit quotient from said data registers, for shifting into said received value said quotient bit QB to generate an updated 2N bit quotient, and for storing said updated 2N bit quotient in said data registers; and an execution controller coupled to said ALU, shift circuitry and logic circuitry for performing a sequence of predefined instructions in a sequence of instruction cycles to generate and store said updated 2N bit quotient in said data registers, including repeatedly executing a predefined set of instructions that cause said ALU and logic circuitry to generate said operation bit value QOP and quotient bit QB, to update said first portion of said dividend in accordance with said operation bit value QOP, to shift said quotient bit QB into said 2N bit quotient to generate said updated 2N bit quotient and to store said updated 2N bit quotient in said data registers, and to transfer one bit from said second portion of said dividend value into said first portion of said dividend value; whereby each execution of said set of instructions generates a quotient bit and transfers one bit of said dividend from said second portion to said first portion of said dividend.

Claim 3

The double precision division circuit of claim 1, wherein said execution controller, when executing a first one of predefined set of instructions, transfers said one bit from said second portion of said dividend value into a carry bit register associated with said ALU, and when executing a second one of said predefined set of instructions, transfers said one bit from said carry bit register into said first portion of said dividend value.

Claim 4

A double precision division circuit, comprising: a data bus having a data path N bits wide; data registers, each storing a 2N bit value, wherein first and second ones of said data registers respectively store upper and lower halves of a signed double precision 4N bit dividend, a third one of said data registers stores a signed 2N bit divisor, and a fourth one of said data registers stores a signed 2N bit quotient; said data registers coupled to said data bus for transferring data values to and from said data registers; said 2N bit value stored by each data register including a sign bit; an arithmetic logic unit (ALU) coupled to said data registers for receiving source values from said first and third data registers, and for performing specified arithmetic operations to generate an output value having a sign bit; logic circuitry coupled to said ALU for receiving the sign bit of the divisor value and the sign bit of the output value generated by said ALU and for generating an operation bit value QOP and a quotient bit QB from said sign bits in accordance with predefined criteria; first, second and third bit registers for storing said operation bit QOP, quotient bit QB, and a data bit, respectively; a bit processor unit (BPU) for receiving the value stored in said fourth data register, for shifting said received value and inserting said quotient bit QB stored in said second bit register into said received value to generate an updated 2N bit quotient, and for storing said updated 2N bit quotient in said fourth data register; and an execution controller coupled to said ALU, BPU and logic circuitry for performing a sequence of predefined instructions in a sequence of instruction cycles to generate and store said updated 2N bit quotient in said fourth data register, including alternately executing a division instruction and a rotate instruction multiple times, wherein said division instruction causes said ALU and logic circuitry to generate said operation bit value QOP and quotient bit QB, to store said QOP and QB values in said first and second bit registers, and to shift said data bit stored in said third bit register into said 2N bit value stored in said first data register, and causes said BPU to insert said quotient bit QB stored in said second bit register during a previous execution of said division instruction into said updated 2N bit quotient and to store said updated 2N bit quotient in said fourth data register; and wherein said rotate instruction causes one of said ALU and BPU to rotate said 2N bit value stored in said second data register and to store a predefined bit of said 2N bit value stored in said second data register in said third bit register; whereby in alternating instruction cycles a quotient bit is generated and one bit of said dividend is transferred from said second data register into said first data register.

Claim 5

A double precision division circuit, comprising: a data bus having a data path N bits wide; data registers, each storing a 2N bit value, wherein first and second ones of said data registers respectively store upper and lower halves of a signed double precision 4N bit dividend, a third one of said data registers stores a signed 2N bit divisor, and a fourth one of said data registers stores a signed 2N bit quotient; said data registers coupled to said data bus for transferring data values to and from said data registers; said 2N bit value stored by each data register including a sign bit; an arithmetic logic unit (ALU) coupled to said data registers for receiving source values from said first and third data registers, and for performing specified arithmetic operations to generate an output value having a sign bit; logic circuitry coupled to said ALU for receiving the sign bit of the divisor value and the sign bit of the output value generated by said ALU and for generating an operation bit value QOP and a quotient bit QB from said sign bits in accordance with predefined criteria; first, second and third bit registers for storing said operation bit QOP, quotient bit QB, and a data bit, respectively; a bit processor unit (BPU) for receiving the value stored in said fourth data register, for shifting said received value and inserting said quotient bit QB stored in said second bit register into said received value to generate an updated 2N bit quotient, and for storing said updated 2N bit quotient in said fourth data register; and an execution controller coupled to said ALU, BPU and logic circuitry for performing a sequence of predefined instructions in a sequence of instruction cycles to generate and store said updated 2N bit quotient in said fourth data register, including alternately executing a division instruction and a rotate instruction multiple times, wherein said division instruction causes said ALU and logic circuitry to generate said operation bit value QOP and quotient bit QB, to store said QOP and QB values in said first and second bit registers, and to shift said data bit stored in said third bit register into said 2N bit value stored in said first data register, and causes said BPU to insert said quotient bit QB stored in said second bit register during a previous execution of said division instruction into said updated 2N bit quotient and to store said updated 2N bit quotient in said fourth data register; and wherein said rotate instruction causes one of said ALU and BPU to rotate said 2N bit value stored in said second data register and to store a predefined bit of said 2N bit value stored in said second data register in said third bit register; whereby in alternating instruction cycles a quotient bit is generated and one bit of said dividend is transferred from said second data register into said first data register.

Claim 6

The double precision division circuit of claim 3, wherein said first bit register is a carry bit register used by said ALU to store a carry bit.

Claim 9

The method of claim 5, wherein said step of performing a sequence of predefined instructions includes transferring said one bit from said second portion of said dividend value into a carry bit register associated with said ALU when executing a first one of said predefined set of instructions and transferring said one bit from said carry bit register into said first portion of said dividend value when executing a second one of said predefined set of instructions.

Claim 12

The method of claim 7, wherein said first bit register is a carry bit register used by said ALU to store a carry bit.