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US5430357A Expired / Lapsed US ⏱️ 0.0 years remaining

Uniformity correction signal generating apparatus for display image

Assignee: Hitachi Ltd
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Filing: 1994-03-10
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Granted: 1995-07-04
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Expires: 2014-03-10
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Abstract

Abstract A uniformity correction signal generating apparatus includes a horizontal address signal generating unit and a vertical address signal generating unit for generating address signals (X) and (Y, y) having one-to-one correspondence to a position on a display screen of a display unit, respectively. Upper and lower adjacent lattice point data are read out from an E 2 PROM on the basis of the address signals X and Y. Interpolated correction data are obtained on the basis of the upper and lower lattice point data and vertical lower address coordinates y. The apparatus is suitable for an auto-scan type display unit and can correct the uniformity for gradation and focus by using the inexpensive E 2 PROM without need of a large capacity expensive E 2 PROM.

Inventors

  • 👤 Masanori Ogino
  • 👤 Takashi Itoh
  • 👤 Miyuki Ikeda
  • 👤 Toshiyuki Kimoto
  • 👤 Satoshi Ohtomo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 18:00
CPC Classifications
G; G09; G09G; G09G1/00; G09G1/06; G09G1/14; G09G1/16; G09G1/165; H; H04; H04N; H04N3/00; H04N3/10; H04N3/16; H04N3/22; H04N3/23; H04N3/233; H04N3/2335; H04N3/27; G09G2320/00; G09G2320/06; G09G2320/0693

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 195 words
A uniformity correction signal generating apparatus comprising: vertical address signal generating means for generating an address signal having at least one-to-one correspondence to position coordinates in a vertical direction on a display screen of a display unit, said address signal including an upper address signal Y and a lower address signal y; memory means for storing a correction data corresponding to each value of said upper address signal Y, a correction data D(Y) corresponding to an address Y of said memory means being stored in a location of said address Y of said memory means; and ROM means for vertical interpolation for producing a correction data D(Y) and the lower address signal y, the correction data stored in said memory means being interpolated on the basis of at least 9 correction data values in a 3×3 macro lattice points on said screen, using a hierarchically structured interpolation polynomial expression, wherein a degree of said interpolation polynomial expression is the zeroth degree for a center of said screen, the second degree for each center of four peripheral sides of said screen and the fourth degree of address coordinates for each of four corners of said screen.
Claim 2
Dependent Claim 195 words
A uniformity correction signal generating apparatus comprising: vertical address signal generating means for generating an address signal having at least one-to-one correspondence to position coordinates in a vertical direction on a display screen of a display unit, said address signal including an upper address signal Y and a lower address signal y; memory means for storing a correction data corresponding to each value of said upper address signal Y, a correction data D(Y) corresponding to an address Y of said memory means being stored in a location of said address Y of said memory means; and ROM means for vertical interpolation for producing a correction data D(Y) and the lower address signal y, the correction data stored in said memory means being interpolated on the basis of at least 9 correction data values in a 3×3 macro lattice points on said screen, using a hierarchically structured interpolation polynomial expression, wherein a degree of said interpolation polynomial expression is the zeroth degree for a center of said screen, the second degree for each center of four peripheral sides of said screen and the fourth degree of address coordinates for each of four corners of said screen.
Claim 3
Dependent Claim 63 words
A uniformity correction signal generating apparatus according to claim 1, wherein said vertical address signal generating means is configured by digitizing a vertical deflection current proportional value of the CRT display unit by means of an A/D converter and said apparatus further comprising switch means for replacing an output of said interpolation ROM means by a constant value during a vertical retrace period.
Claim 4
Dependent Claim 91 words
A uniformity correction signal generating apparatus according to claim 1, further comprising horizontal address signal generating means for generating a horizontal address signal and including sawtooth wave generating means for generating a sawtooth wave of a horizontal period and an A/D converter, a retrace period of the sawtooth wave generated by said sawtooth wave generating means being ΔT shorter than a horizontal retrace period of the display unit, a value of said ΔT being selected to be equal to about two times a delay time of a correction signal transmission circuit.
Claim 5
Dependent Claim 53 words
A uniformity correction signal generating apparatus according to claim 1, wherein said vertical address signal generating means comprises a phase detection circuit, a voltage controlled oscillator and a programmable counter, and a start point and an end point of counting of said programmable counter are proportional to a vertical size of the screen.
Claim 6
Dependent Claim 65 words
A uniformity correction signal generating apparatus according to claim 1, wherein said vertical address signal generating means comprises a counter for counting actual scanning lines and conversion means for converting an output of said counter into universal coordinates, and said conversion means performs conversion so that any one section of said upper address signal Y is associated with a substantially equal distance on the screen.

References Cited (Backward Citations)

US4203054A Cited
US4422019A Cited
US4980614A Cited
US4871948A Cited
US5216497A Cited
US5194783A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-07-03 1999-01-02 1999-07-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-07-03 2003-01-02 2003-07-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-07-03 2007-01-02 2007-07-04 $7700.00 Window Closed / Lapsed

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