US5430488A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Image signal processing apparatus for converting to frame format rastered image data which is supplied in field format but which originated in frame format
Assignee: Sony United Kingdom Ltd
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Filing: 1992-07-08
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Granted: 1995-07-04
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Expires: 2012-07-08
Abstract
Abstract An image signal processing system is described in which image data in an interlaced format is converted to full frame format prior to application of any vertical processing, A swing buffer 40 is employed with Field 0 being written into the even addresses of a DRAM 44 forming one side of the swing buffer under control of an write controller 48. Field 1 is written into the odd addresses, The data in full frame format is read from consecutive addresses in the DRAM 44 into a signal processing engine 62 whilst the next frame is being written into the DRAM 46 forming the other arm of the swing buffer 40. This arrangement allows data that was captured in full frame format to be vertically processed in full frame format thereby preserving its vertical resolution. The full frame image data was converted out of full frame format prior to receipt by the image processing system for compatibility with hardware developed for interlaced format data.
Inventors
- 👤 David J. Hedley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:20
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/01; H04N7/0117; H04N7/012
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
171 words
An image signal processing apparatus for receiving rastered image data supplied thereto in interlaced field format, said rastered image data being of the type that is generated in frame format and then converted into interlaced field format, said apparatus comprising an input memory, for receiving and storing the supplied rastered image data; an input address generator for controlling addressing of said input memory, said input address generator generating memory addresses at which the received rastered image data is stored and having its least significant bit set to a first value throughout reception of a first field of said received rastered image data and set to a second value throughout reception of a second field of said received rastered image data; an input memory reader for reading out the stored rastered image data in frame format from said input memory; and means for effecting signal processing using successive lines of rastered image data in frame format as read from said input memory to produce processed image data for subsequent frame format display.
Claim 2
Dependent Claim
171 words
An image signal processing apparatus for receiving rastered image data supplied thereto in interlaced field format, said rastered image data being of the type that is generated in frame format and then converted into interlaced field format, said apparatus comprising an input memory, for receiving and storing the supplied rastered image data; an input address generator for controlling addressing of said input memory, said input address generator generating memory addresses at which the received rastered image data is stored and having its least significant bit set to a first value throughout reception of a first field of said received rastered image data and set to a second value throughout reception of a second field of said received rastered image data; an input memory reader for reading out the stored rastered image data in frame format from said input memory; and means for effecting signal processing using successive lines of rastered image data in frame format as read from said input memory to produce processed image data for subsequent frame format display.
Claim 3
Dependent Claim
19 words
An image signal processing apparatus as claimed in claim 1, wherein said input memory comprises a swing buffer memory.
Claim 4
Dependent Claim
34 words
An image signal processing apparatus as claimed in claim 1, said means for effecting signal processing comprising a digital video effects system operable for processing rastered image data at frame rate and field rate.
Claim 5
Dependent Claim
114 words
An image signal processing apparatus for receiving rastered image data supplied thereto in interlaced field format, said rastered image data being of the type that is generated in frame format and then converted into interlaced field format, said apparatus comprising: an input memory for receiving and storing the supplied rastered image data; an input memory reader for reading out from said input memory said rastered image data in frame format as two halves of a full frame separated by a blanking period; and means for effecting signal processing using successive lines of rastered image data in frame format as read from said input memory to produce processed image data for subsequent frame format display.
Claim 6
Dependent Claim
114 words
An image signal processing apparatus for receiving rastered image data supplied thereto in interlaced field format, said rastered image data being of the type that is generated in frame format and then converted into interlaced field format, said apparatus comprising: an input memory for receiving and storing the supplied rastered image data; an input memory reader for reading out from said input memory said rastered image data in frame format as two halves of a full frame separated by a blanking period; and means for effecting signal processing using successive lines of rastered image data in frame format as read from said input memory to produce processed image data for subsequent frame format display.
Claim 7
Dependent Claim
41 words
An image signal processing apparatus as claimed in claim 4, wherein said means for effecting signal processing utilises data values from different raster lines held within data value stores, and said data value stores are write disabled during said blanking period.
Claim 8
Dependent Claim
21 words
An image signal processing system as claimed in claim 5, wherein said means for effecting signal processing includes a vertical filter.
Claim 9
Dependent Claim
57 words
An image data processing apparatus as claimed in claim 4, in which said input memory is operable to receive rastered image data in interlaced field format being rastered image data generated in a rastered 30 Hz frame format and converted prior to reception by said image data processing apparatus into a rastered 60 Hz interlaced video format.
Claim 10
Dependent Claim
140 words
An image data processing apparatus for receiving rastered image data supplied thereto in interlaced field format, said rastered image data being of the type that is generated in frame format and then converted into interlaced field format, said apparatus comprising: an input memory for receiving and storing the supplied rastered image data, an input memory reader for reading out the stored rastered image data in frame format from said input memory, means for effecting signal processing using successive lines of rastered image data in frame format as read from said input memory to produce processed image data for subsequent frame format display, an output memory for receiving the processed image data in frame format from said means for effecting signal processing, and an output memory reader for reading and outputting processed image data in interlaced format from said output memory.
Claim 11
Dependent Claim
140 words
An image data processing apparatus for receiving rastered image data supplied thereto in interlaced field format, said rastered image data being of the type that is generated in frame format and then converted into interlaced field format, said apparatus comprising: an input memory for receiving and storing the supplied rastered image data, an input memory reader for reading out the stored rastered image data in frame format from said input memory, means for effecting signal processing using successive lines of rastered image data in frame format as read from said input memory to produce processed image data for subsequent frame format display, an output memory for receiving the processed image data in frame format from said means for effecting signal processing, and an output memory reader for reading and outputting processed image data in interlaced format from said output memory.
Claim 12
Dependent Claim
19 words
An image signal processing apparatus as claimed in claim 8, wherein said output memory comprises a swing buffer memory.
Claim 13
Dependent Claim
81 words
An image signal processing apparatus as claimed in claim 8, further comprising an output address generator for controlling addressing of said output memory, said output address generator having its least significant bit set to a first value during reading of a first field of said processed image data in interlaced field format from said output memory and set to a second value during reading of a second field of said processed image data in interlaced field format from said output memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-03 | 1999-01-02 | 1999-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-03 | 2003-01-02 | 2003-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-03 | 2007-01-02 | 2007-07-04 | $7700.00 | Window Closed / Lapsed |