Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a bit line; a word line; a plate electrode; a ferroelectric capacitor having a first electrode and a second electrode, said second electrode being coupled to said plate electrode; a MOS transistor, the source of which is coupled to said first electrode, the gate is coupled to said word line and the drain is coupled to said bit line; and an adjusting capacitor for adjusting bit line capacitance coupled to said bit line, wherein said adjusting capacitor comprises a ferroelectric film.

Claim 3

The semiconductor memory device of claim 1 wherein a component system of a material of said ferroelectric film is identical to that of a material of said ferroelectric capacitor.

Claim 4

The semiconductor memory device of claim 1 wherein a shape and a size of said adjusting capacitor are about the same as a shape and a size of said ferroelectric capacitor.

Claim 5

A semiconductor memory device comprising: a first bit line and a second bit line; a word line; a plate electrode; a ferroelectric capacitor having a first electrode and a second electrode, said second electrode being coupled to said plate electrode; a MOS transistor the source of which is coupled to said first electrode, the gate is coupled to said word line and the drain is coupled to said first bit line; an adjusting capacitor for adjusting bit line capacitance coupled to said first bit line; and a sense amplifier to which said first bit line and said second bit line are coupled; wherein said adjusting capacitor has a capacitance value decided in such a way that a potential difference between a reading potential of said first bit line and a reading potential of said second bit line is not less than a minimum operating voltage of said sense amplifier.

Claim 6

A semiconductor memory device comprising: a first bit line and a second bit line; a word line; a plate electrode; a ferroelectric capacitor having a first electrode and a second electrode, said second electrode being coupled to said plate electrode; a MOS transistor the source of which is coupled to said first electrode, the gate is coupled to said word line and the drain is coupled to said first bit line; an adjusting capacitor for adjusting bit line capacitance coupled to said first bit line; and a sense amplifier to which said first bit line and said second bit line are coupled; wherein said adjusting capacitor has a capacitance value decided in such a way that a potential difference between a reading potential of said first bit line and a reading potential of said second bit line is not less than a minimum operating voltage of said sense amplifier.

Claim 7

The semiconductor memory device of claim 4 wherein said capacitance value is a minimal value.

Claim 8

A semiconductor memory device comprising: a first bit line and a second bit line; a word line; a plate electrode; a signal line; a ferroelectric capacitor having a first electrode and a second electrode, said second electrode being coupled to said plate electrode; a MOS transistor the source of which is coupled to said first electrode, the gate is coupled to said word line and the drain is coupled to said first bit line; a first adjusting capacitor and a second adjusting capacitor for adjusting bit line capacitance, said first adjusting capacitor being coupled to said first bit line, and said second adjusting capacitor being coupled to said second bit line; and a sense amplifier to which said first bit line and said second bit line are coupled.

Claim 9

A semiconductor memory device comprising: a first bit line and a second bit line; a word line; a plate electrode; a signal line; a ferroelectric capacitor having a first electrode and a second electrode, said second electrode being coupled to said plate electrode; a MOS transistor the source of which is coupled to said first electrode, the gate is coupled to said word line and the drain is coupled to said first bit line; a first adjusting capacitor and a second adjusting capacitor for adjusting bit line capacitance, said first adjusting capacitor being coupled to said first bit line, and said second adjusting capacitor being coupled to said second bit line; and a sense amplifier to which said first bit line and said second bit line are coupled.

Claim 10

The semiconductor memory device of claim 6 wherein said first adjusting capacitor has a pair of electrodes, and a logical voltage of one of said electrodes and a logical voltage of the other of said electrodes are different from each other when said semiconductor memory device is on standby.

Claim 11

The semiconductor memory device of claim 6 wherein said first adjusting capacitor and said second adjusting capacitor include of a plurality of capacitors respectively.

Claim 12

The semiconductor memory device of claim 8 wherein each of said plurality of capacitors has a capacitance value about equal to that of said ferroelectric capacitor.

Claim 13

The semiconductor memory device of claim 8 wherein a separating means is provided between at least one of said plurality of capacitors and said first and second bit line.

Claim 14

The semiconductor memory device of claim 6 wherein said first adjusting capacitor and said second adjusting capactior comprise a ferroelectric film.

Claim 15

A method for initializing said first adjusting capacitor and said second adjusting capacitor of the semiconductor memory device of claim 11 comprising the steps of applying a logical voltage "L" to said first bit line and a logical voltage "H" to said second bit line, and applying a logical voltage "H" to said first bit line and a logical voltage "L" to said second bit line.

Claim 16

A method for initializing said first adjusting capacitor and said second adjusting capacitor of the semiconductor memory device of claim 11 comprising the step of applying a logical voltage "H" to said first bit line and said second bit line.

Claim 17

The semiconductor memory device of claim 3 wherein said first adjusting capacitor has a pair of electrodes, and a logical voltage of one of said electrodes and a logical voltage of the other of said electrodes are both at "L" when said semiconductor memory device is on standby.

Claim 18

A method for initializing said first adjusting capacitor and said second adjusting capacitor of the semiconductor memory device of claim 14 comprising the steps of applying a logical voltage "L" to said first bit line and a logical voltage "H" to said second bit line, and applying a logical voltage "H" to said first bit line and a logical voltage "L" to said second bit line.

Claim 19

A method for initializing said first adjusting capacitor and said second adjusting capacitor of the semiconductor memory device of claim 14 comprising the step of applying a logical voltage "H" to said first bit line and said second bit line.

Claim 20

A semiconductor memory device comprising: a first bit line and a second bit line forming a pair; a first word line and a second word line; a first plate electrode and a second plate electrode; a signal line; a first ferroelectric capacitor coupled to said first plate electrode and a second ferroelectric capacitor electrode coupled to said second plate electrode; a first MOS transistor the source of which is coupled to said first ferroelectric capacitor, the gate is coupled to said first word line and the drain is coupled to said first bit line; a second MOS transistor the source of which is coupled to said second ferroelectric capacitor, the gate is coupled to said second word line and the drain is coupled to said second bit line; a first adjusting capacitor coupled between said first bit line and said signal line; a second adjusting capacitor coupled between said second bit line and said signal line; and a sense amplifier coupled to said first bit line and said second bit line; a capacitance value of said second ferroelectric capacitor being found between a capacitance value of said first ferroelectric capacitor at the time when a logical voltage "H" is written in said first ferroelectric capacitor and a capacitance value of said first ferroelectric capacitor at the time when a logical voltage "L" is written in said first ferroelectric capacitor.

Claim 21

A semiconductor memory device comprising: a first bit line and a second bit line forming a pair; a first word line and a second word line; a first plate electrode and a second plate electrode; a signal line; a first ferroelectric capacitor coupled to said first plate electrode and a second ferroelectric capacitor electrode coupled to said second plate electrode; a first MOS transistor the source of which is coupled to said first ferroelectric capacitor, the gate is coupled to said first word line and the drain is coupled to said first bit line; a second MOS transistor the source of which is coupled to said second ferroelectric capacitor, the gate is coupled to said second word line and the drain is coupled to said second bit line; a first adjusting capacitor coupled between said first bit line and said signal line; a second adjusting capacitor coupled between said second bit line and said signal line; and a sense amplifier coupled to said first bit line and said second bit line; a capacitance value of said second ferroelectric capacitor being found between a capacitance value of said first ferroelectric capacitor at the time when a logical voltage "H" is written in said first ferroelectric capacitor and a capacitance value of said first ferroelectric capacitor at the time when a logical voltage "L" is written in said first ferroelectric capacitor.

Claim 22

The semiconductor memory device of claim 17 wherein said first adjusting capacitor and said second adjusting capacitor have respectively a capacitance value decided in such a way that a potential difference between a reading potential of said first bit line and a reading potential of said second bit line at the time when the logical voltage "H" or "L" is written in said first ferroelectric capacitor is not less than a minimum operating voltage of said sense amplifier.

Claim 23

A semiconductor memory device comprising: a plurality of pairs of a first bit line and a second bit line arranged in columns, a plurality of word lines arranged in rows, a plurality of plate electrodes, a plurality of sense amplifiers coupled to said first bit line and said second bit line, a plurality of pairs of a first adjusting capacitor coupled to said first bit line and a second adjusting capacitor coupled to said second bit line, respectively, and a plurality of memory cells arranged in rows and columns, each memory cell comprising a first MOS transistor, a second MOS transistor, a first ferroelectric capacitor having a pair of electrodes and a second ferroelectric capacitor having a pair of electrodes, the drain of said first MOS transistor being coupled to said first bit line and the drain of said second MOS transistor being coupled to said second bit line respectively, the source of said first MOS transistor being coupled to one electrode on one side of said first ferroelectric capacitor and the source of said second MOS transistor being coupled to one electrode on one side of said second ferroelectric capacitor, the other electrode of said first ferroelectric capacitor and the other electrode of said second ferroelectric capacitor being coupled to said plate electrode.

Claim 24

A semiconductor memory device comprising: a plurality of pairs of a first bit line and a second bit line arranged in columns, a plurality of word lines arranged in rows, a plurality of plate electrodes, a plurality of sense amplifiers coupled to said first bit line and said second bit line, a plurality of pairs of a first adjusting capacitor coupled to said first bit line and a second adjusting capacitor coupled to said second bit line, respectively, and a plurality of memory cells arranged in rows and columns, each memory cell comprising a first MOS transistor, a second MOS transistor, a first ferroelectric capacitor having a pair of electrodes and a second ferroelectric capacitor having a pair of electrodes, the drain of said first MOS transistor being coupled to said first bit line and the drain of said second MOS transistor being coupled to said second bit line respectively, the source of said first MOS transistor being coupled to one electrode on one side of said first ferroelectric capacitor and the source of said second MOS transistor being coupled to one electrode on one side of said second ferroelectric capacitor, the other electrode of said first ferroelectric capacitor and the other electrode of said second ferroelectric capacitor being coupled to said plate electrode.

Claim 25

A semiconductor memory device comprising: a pair of a first bit line and a second bit line; a word line; a plate electrode; a ferroelectric capacitor having a first electrode and a second electrode, said second electrode being coupled to said plate electrode; a MOS transistor the source of which is coupled to said first electrode, the gate is coupled to said word line and the drain is coupled to said first bit line; and a sense amplifier to which said first bit line and said second bit line are coupled; wherein said ferroelectric capacitor has a capacitance value decided in such a way that a potential difference between a reading potential of said first bit line and a reading potential of said second bit line is not less than a minimum operating voltage of said sense amplifier.

Claim 26

A semiconductor memory device comprising: a pair of a first bit line and a second bit line; a word line; a plate electrode; a ferroelectric capacitor having a first electrode and a second electrode, said second electrode being coupled to said plate electrode; a MOS transistor the source of which is coupled to said first electrode, the gate is coupled to said word line and the drain is coupled to said first bit line; and a sense amplifier to which said first bit line and said second bit line are coupled; wherein said ferroelectric capacitor has a capacitance value decided in such a way that a potential difference between a reading potential of said first bit line and a reading potential of said second bit line is not less than a minimum operating voltage of said sense amplifier.

Claim 27

A semiconductor memory device comprising: a first bit line and a second bit line forming a pair; a first word line and a second word line; a first plate electrode and a second plate electrode; a signal line; a first ferroelectric capacitor coupled to said first plate electrode and a second ferroelectric capacitor electrode coupled to said second plate electrode; a first MOS transistor the source of which is coupled to said first ferroelectric capacitor, the gate is coupled to said first word line and the drain is coupled to said first bit line; a second MOS transistor the source of which is coupled to said second ferroelectric capacitor, the gate is coupled to said second word line and the drain is coupled to said second bit line; and a sense amplifier coupled to said first bit line and said second bit line; wherein said first ferroelectric capacitor and said second ferroelectric capacitor have respectively a capacitance value decided in such a way that a potential difference between a reading potential of said first bit line and a reading potential of said second bit line at the time when a logical voltage "H" or "L" is written in said first ferroelectric capacitor is not less than a minimum operating voltage of said sense amplifier.

Claim 28

A semiconductor memory device comprising: a first bit line and a second bit line forming a pair; a first word line and a second word line; a first plate electrode and a second plate electrode; a signal line; a first ferroelectric capacitor coupled to said first plate electrode and a second ferroelectric capacitor electrode coupled to said second plate electrode; a first MOS transistor the source of which is coupled to said first ferroelectric capacitor, the gate is coupled to said first word line and the drain is coupled to said first bit line; a second MOS transistor the source of which is coupled to said second ferroelectric capacitor, the gate is coupled to said second word line and the drain is coupled to said second bit line; and a sense amplifier coupled to said first bit line and said second bit line; wherein said first ferroelectric capacitor and said second ferroelectric capacitor have respectively a capacitance value decided in such a way that a potential difference between a reading potential of said first bit line and a reading potential of said second bit line at the time when a logical voltage "H" or "L" is written in said first ferroelectric capacitor is not less than a minimum operating voltage of said sense amplifier.