Flexible redundancy architecture and fuse download scheme

Claim 2

In an integrated circuit comprising a plurality of circuit elements, some of which may be faulty, which respond to a discrete set of access signals, and a plurality of redundant elements that are programmed to respond to said discrete set of access signals to substitute for faulty ones of said plurality of circuit elements, a redundancy programming method comprising the steps of: testing said integrated circuit to determine which of said plurality of circuit elements are faulty; programming a plurality of sets of non-volatile storage elements, such that at least some of said plurality of sets of non-volatile storage elements store a first plurality of signals that simulate the discrete set of access signals corresponding to a faulty one of said plurality of circuit elements and a second plurality of signals indicating a selected one of said plurality of redundant elements to be substituted for said faulty one of said plurality of circuit elements; and sequentially downloading programmed ones of said plurality of sets of non-volatile storage elements to set selected ones of said plurality of redundant elements to substitute for faulty ones of said plurality of circuit elements when said discrete set of access signals for faulty ones of said plurality of circuit elements are received.

Claim 3

A redundancy system for a memory chip having a plurality of rows of memory cells, comprising: a plurality of rows of redundant memory cells; a plurality of sets of fuses, each set of fuses including a first plurality of fuses storing logic states for selecting one of said plurality of rows of redundant memory cells, and a second plurality of fuses storing logic states indicating a faulty one of said plurality of rows of memory cells; and a fuse downloader for sequentially accessing each of said plurality of sets of fuses, wherein during accessing of a given one of said plurality of sets of fuses said first and second plurality of fuses are accessed serially.

Claim 4

A redundancy system for a memory chip having a plurality of rows of memory cells, comprising: a plurality of rows of redundant memory cells; a plurality of sets of fuses, each set of fuses including a first plurality of fuses storing logic states for selecting one of said plurality of rows of redundant memory cells, and a second plurality of fuses storing logic states indicating a faulty one of said plurality of rows of memory cells; and a fuse downloader for sequentially accessing each of said plurality of sets of fuses, wherein during accessing of a given one of said plurality of sets of fuses said first and second plurality of fuses are accessed serially.

Claim 5

The redundancy system of claim 2, wherein each of said plurality of sets of fuses further includes a fuse indicating that the particular set of fuses has been programmed.

Claim 6

The redundancy system of claim 3, wherein each of said plurality of sets of fuses further includes a second fuse indicating that the particular set of fuses is faulty.

Claim 7

The redundancy system of claim 4, wherein said fuse downloader includes means to bypass further accessing of a given one of said plurality of sets of fuses should either of its first or second fuses indicate that access should be discontinued.

Claim 8

The redundancy system of claim 2, wherein said plurality of rows of redundant memory cells is greater in number than said plurality of sets of fuses.

Claim 9

The redundancy system of claim 2, wherein said plurality of rows of redundant elements are arranged into groups, and wherein said first plurality of fuses includes a first subset of fuses which store logic signals that select which group of said plurality of rows of redundant elements, and a second subset of fuses which store logic signals that select one of said plurality of rows of redundant elements within said selected group.

Claim 10

The redundancy system of claim 7, wherein said fuse downloader accesses and first subset of fuses in a first fuse download cycle, said second subset of fuses in a second fuse download cycle, and said second plurality of fuses in a third fuse download cycle.

Claim 11

The redundancy system of claim 2, further comprising a data/control bus coupled between said fuse downloader and said plurality, of rows of redundant memory cells.

Claim 12

The redundancy system of claim 9, wherein during access of a given one of said plurality of sets of fuses, logic states from said first plurality of fuses are transmitted on a control portion of said data/control bus, anal logic states from said second plurality of fuses are transmitted on a data portion of said bus separate from said control portion of said bus.

Claim 13

In an integrated circuit having a plurality of functional circuit elements, at least one of which may be faulty, and a plurality of redundant circuit elements, a redundancy system comprising: a plurality of redundant decoders, each of which enables a corresponding one of said plurality of redundant circuit elements; storage means for storing first information identifying which of said functional circuit elements is faulty and for storing second information identifying which of said plurality of redundant circuit elements is to be substituted for said faulty one of said functional circuit elements, said storage means comprising a plurality of sets of nonvolatile storage elements, at least some of said plurality of sets being programmed, each of said programmed sets storing said first and second information and also storing third information indicating whether said first and second programmed set is faulty; said storage means further including: a first means for serially accessing all of said plurality of sets of non-volatile storage elements, a second means for bussing information from each of said plurality of sets of nonvolatile storage elements accessed by said first means to said plurality of rows of redundant memory cells, and a third means for controlling said second means so that when a given one of said plurality of sets of nonvolatile storage elements is accessed, signals from said first group of storage elements is transmitted on said second means during a first download cycle, and signals from said second group of storage elements are accessed during a second download cycle; said second information enabling a selected one of said plurality of redundant decoders and said first information causing said enabled redundant decoder to activate said corresponding one of said plurality of redundant circuit elements when said faulty one of said plurality of functional circuit elements is selected for activation.

Claim 14

In an integrated circuit having a plurality of functional circuit elements, at least one of which may be faulty, and a plurality of redundant circuit elements, a redundancy system comprising: a plurality of redundant decoders, each of which enables a corresponding one of said plurality of redundant circuit elements; storage means for storing first information identifying which of said functional circuit elements is faulty and for storing second information identifying which of said plurality of redundant circuit elements is to be substituted for said faulty one of said functional circuit elements, said storage means comprising a plurality of sets of nonvolatile storage elements, at least some of said plurality of sets being programmed, each of said programmed sets storing said first and second information and also storing third information indicating whether said first and second programmed set is faulty; said storage means further including: a first means for serially accessing all of said plurality of sets of non-volatile storage elements, a second means for bussing information from each of said plurality of sets of nonvolatile storage elements accessed by said first means to said plurality of rows of redundant memory cells, and a third means for controlling said second means so that when a given one of said plurality of sets of nonvolatile storage elements is accessed, signals from said first group of storage elements is transmitted on said second means during a first download cycle, and signals from said second group of storage elements are accessed during a second download cycle; said second information enabling a selected one of said plurality of redundant decoders and said first information causing said enabled redundant decoder to activate said corresponding one of said plurality of redundant circuit elements when said faulty one of said plurality of functional circuit elements is selected for activation.