US5434870A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for verifying the authenticity of a circuit board
Assignee: Unisys Corp
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Filing: 1992-04-17
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Granted: 1995-07-18
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Expires: 2012-04-17
Abstract
Abstract Disclosed is an apparatus and method for verifying the authenticity of a circuit board incorporated in a system. The method employs signal representing a unique identifier, such as a serial number and an associated error check code, to identify the circuit board. The identifier signal is passed from the circuit board to the system when the circuit board is initialized. To verify that a circuit board is authentic, the error check code (ECC) represented in the second part of the circuit board's identifier signal is verified. If the ECC is not correct then the circuit board is left unused. Next, the first part of the identifier signal (e.g. the serial number) is compared to the identifier signals for all other circuit boards mounted within the system. If a match of any two identifier signals is found, all circuit boards associated with the common identifier signal are left unused. If no duplicates are found and the ECC was correct, the circuit board is permitted to function.
Inventors
- 👤 Michael K. Benton
- 👤 An Le
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:21
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/006
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
147 words
An apparatus comprising: at least one circuit board port disabled by default; at least one circuit board, coupled with said circuit board port; storage means, residing on said circuit board, for storing an identification code including a code representing a unique identifier and a code representing a first error correction code associated with said unique identifier; reading means, coupled with said circuit board port, for reading said identification code stored in said storage means; verification means, coupled with said reading means, for verifying that said identification code is unique and for calculating a second error correction code from said unique identifier and comparing said first and second error correction codes in determining if said identification code is valid; and control means, coupled with said circuit board port and responsive to said verification means, for enabling said circuit board port if said identification code is unique and valid.
Claim 2
Independent Claim
147 words
An apparatus comprising: at least one circuit board port disabled by default; at least one circuit board, coupled with said circuit board port; storage means, residing on said circuit board, for storing an identification code including a code representing a unique identifier and a code representing a first error correction code associated with said unique identifier; reading means, coupled with said circuit board port, for reading said identification code stored in said storage means; verification means, coupled with said reading means, for verifying that said identification code is unique and for calculating a second error correction code from said unique identifier and comparing said first and second error correction codes in determining if said identification code is valid; and control means, coupled with said circuit board port and responsive to said verification means, for enabling said circuit board port if said identification code is unique and valid.
Claim 3
Dependent Claim
32 words
The apparatus of claim 1 wherein said verification means comprises: memory system; verification software program stored in said memory system; processor coupled with said memory system for executing said verification software program.
Claim 4
Dependent Claim
36 words
The apparatus of claim 2 wherein: said signal representing said error correction code is determined by a method which is the same said method employed to perform error checking within said memory system during normal operation.
Claim 5
Dependent Claim
12 words
The apparatus of claim 1 wherein said storage means includes a PROM.
Claim 6
Dependent Claim
15 words
The apparatus of claim 1 wherein said circuit board comprises a daughter memory circuit board.
Claim 7
Independent Claim
261 words
A method of determining whether a first circuit board which is coupled with an initially disabled first circuit board port in a system is authorized for use in said system comprising the steps of: reading from a storage residing on said first circuit board an identification code, said identification code including a code representing a unique identifier for said circuit board and a code representing a first error correction code associated with said unique identifier; calculating an expected error correction code associated with said unique identifier; comparing said expected error correction code to said first error correction code and not enabling said first circuit board port if said codes are equal; comparing said signal representing a unique identifier to each member of a list of signals representing identifiers of other boards plugged into said system and not enabling said first circuit board port if said code representing a unique identifier is found to equal any member of said list; disabling a second circuit board port if said code representing a unique identifier is found to equal any member of said list wherein a second circuit board which is associated with said member of said list which equaled said code representing a unique identifier is coupled with said second circuit board port; adding said code representing a unique identifier to said list of identifiers for circuit boards plugged into said system; and enabling said first circuit board port if said code representing a unique identifier did not equal any member of said list and said codes representing error correction codes were equal.
Claim 8
Independent Claim
261 words
A method of determining whether a first circuit board which is coupled with an initially disabled first circuit board port in a system is authorized for use in said system comprising the steps of: reading from a storage residing on said first circuit board an identification code, said identification code including a code representing a unique identifier for said circuit board and a code representing a first error correction code associated with said unique identifier; calculating an expected error correction code associated with said unique identifier; comparing said expected error correction code to said first error correction code and not enabling said first circuit board port if said codes are equal; comparing said signal representing a unique identifier to each member of a list of signals representing identifiers of other boards plugged into said system and not enabling said first circuit board port if said code representing a unique identifier is found to equal any member of said list; disabling a second circuit board port if said code representing a unique identifier is found to equal any member of said list wherein a second circuit board which is associated with said member of said list which equaled said code representing a unique identifier is coupled with said second circuit board port; adding said code representing a unique identifier to said list of identifiers for circuit boards plugged into said system; and enabling said first circuit board port if said code representing a unique identifier did not equal any member of said list and said codes representing error correction codes were equal.
Claim 9
Dependent Claim
37 words
The method of claim 6 wherein the method used to calculate said error correction code is determined by a method which is the same said method employed to perform error checking within said system during normal operation.
Claim 10
Independent Claim
133 words
A method of identifying a circuit board coupled with a system via an initially disabled circuit board port, said method comprising the steps of: reading from a storage residing on said circuit board an identification code including a code representing a unique identifier and a code representing a first error correction code associated with said unique identifier; verifying that said identification code is unique within said system; verifying that said identification code is not in error; enabling said circuit board port if said identification code is unique-and not in error; disabling said circuit board port if said identification signal is not unique within said system or if said identification signal is in error; and employing said identification code to report information associated with said circuit board if said circuit board port is enabled.
Claim 11
Independent Claim
133 words
A method of identifying a circuit board coupled with a system via an initially disabled circuit board port, said method comprising the steps of: reading from a storage residing on said circuit board an identification code including a code representing a unique identifier and a code representing a first error correction code associated with said unique identifier; verifying that said identification code is unique within said system; verifying that said identification code is not in error; enabling said circuit board port if said identification code is unique-and not in error; disabling said circuit board port if said identification signal is not unique within said system or if said identification signal is in error; and employing said identification code to report information associated with said circuit board if said circuit board port is enabled.
Claim 12
Dependent Claim
57 words
The method of claim 8 wherein said steps of verifying that said identification signal is not in error comprises the steps of: calculating a signal representing an expected error correction code associated with said unique identifier; comparing said signal representing a calculated error correction code to said signal representing an error correction code read from said storage.
Claim 13
Dependent Claim
34 words
The method of claim 9 wherein the method used to calculate a signal representing an expected error correction code is the same method employed to perform error checking within said system during normal operation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-17 | 1999-01-16 | 1999-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-17 | 2003-01-16 | 2003-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-17 | 2007-01-16 | 2007-07-18 | $7700.00 | Window Closed / Lapsed |