US5434990A
Expired / Lapsed
US
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Method for serially or concurrently addressing n individually addressable memories each having an address latch and data latch
Assignee: Cufer Asset Ltd LLC
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Filing: 1990-08-06
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Granted: 1995-07-18
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Expires: 2010-08-06
Abstract
Abstract A method for reading data from an n-way, set associative cache. n individually addressable memory units are provided, with each of the units storing a plurality of data elements. All n of the units are concurrently addressed to transfer a data element from each of the units to a respective latch, and one of such data elements is selectively transferred from one of the latches. The units are then serially addressed in a predetermined pattern to sequentially transfer data elements out of the units.
Inventors
- 👤 Robert B. Moussavi
- 👤 Jackson L. Ellis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:44
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0864; G06F12/0844; G06F12/0846; G06F12/0851; G06F12/10; G06F12/1027; G06F12/1045; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
141 words
A method for transferring data from an n-way, set associative cache having n individually addressable memory units, wherein each of said memory units stores a plurality of data elements, comprising: concurrently addressing all n of said units to transfer a data element from each of said units to a respective data latch; selectively transferring a first data element from one of said data latches; and serially addressing said memory units to sequentially transfer data elements out of respective ones of said memory units; wherein each memory unit has an address latch associated therewith, and wherein during said serially addressing step said memory units are addressed one at a time, further comprising during said serially addressing step; latching an address in the address latch associated with one of said memory units when a different one of said memory units is being addressed.
Claim 2
Independent Claim
141 words
A method for transferring data from an n-way, set associative cache having n individually addressable memory units, wherein each of said memory units stores a plurality of data elements, comprising: concurrently addressing all n of said units to transfer a data element from each of said units to a respective data latch; selectively transferring a first data element from one of said data latches; and serially addressing said memory units to sequentially transfer data elements out of respective ones of said memory units; wherein each memory unit has an address latch associated therewith, and wherein during said serially addressing step said memory units are addressed one at a time, further comprising during said serially addressing step; latching an address in the address latch associated with one of said memory units when a different one of said memory units is being addressed.
Claim 3
Independent Claim
254 words
A method for transferring data from an n-way, set associative cache having n individually addressable memory units, wherein each of said memory units stores a plurality of data elements, and wherein each of said memory units has an enable line, comprising: arranging said data elements in each of said memory units so that a single address identifies a data element in each memory unit from a single set and different way; arranging said data elements in each of said memory units so that within each memory unit n data elements having sequential addresses are from n different ways; concurrently addressing all n of said units to transfer a data element from each of said units to a respective data latch; selectively transferring a first data element from one of said data latches; serially addressing said memory units in a predetermined pattern to sequentially transfer a data element from each of said memory units to a respective one of said data latches; further transferring each of said sequentially transferred data element from its respective data latch; and precharging the enable line for one of said memory units when another of said memory units is being serially addressed; wherein each memory unit has an address latch associated therewith, and wherein during said serially addressing step said memory units are addressed one at a time, further comprising during said serially addressing step: latching an address in the address latch associated with one of said memory units when a different one of said memory units is being addressed.
Claim 4
Independent Claim
254 words
A method for transferring data from an n-way, set associative cache having n individually addressable memory units, wherein each of said memory units stores a plurality of data elements, and wherein each of said memory units has an enable line, comprising: arranging said data elements in each of said memory units so that a single address identifies a data element in each memory unit from a single set and different way; arranging said data elements in each of said memory units so that within each memory unit n data elements having sequential addresses are from n different ways; concurrently addressing all n of said units to transfer a data element from each of said units to a respective data latch; selectively transferring a first data element from one of said data latches; serially addressing said memory units in a predetermined pattern to sequentially transfer a data element from each of said memory units to a respective one of said data latches; further transferring each of said sequentially transferred data element from its respective data latch; and precharging the enable line for one of said memory units when another of said memory units is being serially addressed; wherein each memory unit has an address latch associated therewith, and wherein during said serially addressing step said memory units are addressed one at a time, further comprising during said serially addressing step: latching an address in the address latch associated with one of said memory units when a different one of said memory units is being addressed.
Claim 5
Dependent Claim
65 words
The method of claim 2 wherein said step of concurrently addressing said units includes: generating a first address having a tag address and an element address; and using said element address to address all of said units while comparing said tag address to addresses in a tag store to determine if said first data element is in said cache and which way contains said element.
Claim 6
Dependent Claim
36 words
The method of claim 3 further comprising: generating a signal based on the tag address comparison and using said signal to selectively enable the transfer of the first data element from said one of said latches.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-17 | 1999-01-16 | 1999-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-17 | 2003-01-16 | 2003-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-17 | 2007-01-16 | 2007-07-18 | $7700.00 | Window Closed / Lapsed |