US5436199A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pillar alignment and formation process
Assignee: Texas Instruments Inc
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Filing: 1993-06-22
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Granted: 1995-07-25
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Expires: 2013-06-22
Abstract
Abstract A process for the formation of pillars (28) in connection with the fabrication of a semiconductor device (10) is disclosed. The process first aligns a lead pattern (30) with an existing structure (24) in the semiconductor device (10). Next, the process aligns a pillar pattern (32) with the lead pattern (30). These two patterns (30, 32) are then transferred downward into respective conductive layers (26, 28) of the semiconductor device (10). An insulating layer (34) is deposted over the conductive layers (26, 28) and etched-back to expose a portion of the pillar (28). A conductive layer (42) is applied over the exposed pillar (28).
Inventors
- 👤 Jeffrey E. Brighton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:28
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; H10W20/0633; H10W20/069; H10W20/0693
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
142 words
A method of interconnecting first and second conductive layers through an intermediate insulating layer, said method comprising the steps of: forming said first conductive layer overlying a substrate which has an alignment structure thereon, a conductive pillar layer overlying said first layer, and a barrier layer overlying said pillar layer; removing portions of said pillar and barrier layers to define a first layer pattern in said pillar and barrier layers, said first layer pattern being aligned with said alignment structure; removing portions of said barrier layer to define a pillar pattern in said barrier layer, said pillar pattern being aligned with said first layer pattern; transferring said first layer pattern to said first layer and said pillar pattern to said pillar layer; forming said insulating layer overlying said first layer; and forming said second conductive layer overlying said insulating and pillar layers.
Claim 2
Independent Claim
142 words
A method of interconnecting first and second conductive layers through an intermediate insulating layer, said method comprising the steps of: forming said first conductive layer overlying a substrate which has an alignment structure thereon, a conductive pillar layer overlying said first layer, and a barrier layer overlying said pillar layer; removing portions of said pillar and barrier layers to define a first layer pattern in said pillar and barrier layers, said first layer pattern being aligned with said alignment structure; removing portions of said barrier layer to define a pillar pattern in said barrier layer, said pillar pattern being aligned with said first layer pattern; transferring said first layer pattern to said first layer and said pillar pattern to said pillar layer; forming said insulating layer overlying said first layer; and forming said second conductive layer overlying said insulating and pillar layers.
Claim 3
Dependent Claim
46 words
A method as claimed in claim 1 additionally comprising the step of applying a material over said insulating layer so that said material has a substantially planar surface and so that the etch rate of said material substantially equals the etch rate of said insulating layer.
Claim 4
Dependent Claim
25 words
A method as claimed in claim 2 wherein said insulating layer is a plasma oxide formed sufficiently thick to cover said first and pillar layers.
Claim 5
Dependent Claim
26 words
A method as claimed in claim 2 wherein said material is a photoresist, and said material applying step includes a spin-on operation to planarize said photoresist.
Claim 6
Dependent Claim
31 words
A method as claimed in claim 1 additionally comprising the step of forming each of said first and pillar layers to comprise a lower barrier layer and an upper metal layer.
Claim 7
Independent Claim
169 words
A method of forming a pillar in a semiconductor device having an alignment structure thereon, a first barrier layer overlying said alignment structure, a bottom conductive layer overlying said first barrier layer, a second barrier layer overlying said bottom conductive layer, a top conductive layer overlying said second barrier layer, and a third barrier layer overlying said top conductive layer, said method comprising the steps of: defining a lead pattern in said third barrier layer, said top conductive layer, and said second barrier layer, said lead pattern being laterally positioned within a predetermined tolerance of said alignment structure; defining a pillar pattern in said third barrier layer, said pillar pattern being laterally positioned within said predetermined tolerance of said lead pattern; simultaneously etching portions of said top and bottom conductive layers using an etchant which etches entirely through said conductive layers without etching through said barrier layers; and simultaneously etching portions of said first, second, and third barrier layers using said top and bottom conductive layers as etch stops.
Claim 8
Independent Claim
169 words
A method of forming a pillar in a semiconductor device having an alignment structure thereon, a first barrier layer overlying said alignment structure, a bottom conductive layer overlying said first barrier layer, a second barrier layer overlying said bottom conductive layer, a top conductive layer overlying said second barrier layer, and a third barrier layer overlying said top conductive layer, said method comprising the steps of: defining a lead pattern in said third barrier layer, said top conductive layer, and said second barrier layer, said lead pattern being laterally positioned within a predetermined tolerance of said alignment structure; defining a pillar pattern in said third barrier layer, said pillar pattern being laterally positioned within said predetermined tolerance of said lead pattern; simultaneously etching portions of said top and bottom conductive layers using an etchant which etches entirely through said conductive layers without etching through said barrier layers; and simultaneously etching portions of said first, second, and third barrier layers using said top and bottom conductive layers as etch stops.
Claim 9
Dependent Claim
30 words
A method as claimed in claim 6 wherein both of said etching steps include a reactive ion etching operation so that substantially vertical walls are formed during said etching steps.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-24 | 1999-01-23 | 1999-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-24 | 2003-01-23 | 2003-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-24 | 2007-01-23 | 2007-07-25 | $7700.00 | Window Closed / Lapsed |