US5437016A
Expired / Lapsed
US
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Apparatus and method for translating logical addresses for virtual machines
Assignee: Hitachi Ltd
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Filing: 1992-07-06
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Granted: 1995-07-25
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Expires: 2012-07-06
Abstract
Abstract An absolute address translated from a logical address input by a user program by an address translation circuit and a prefix translation circuit, is compared with contents of a virtual processor prefix register. On the basis of the comparison result, a multi-processor field of a translation lookaside buffer (TLB) has a value indicating whether or not the entry corresponds to an area common among virtual processors. The MP field of the TLB is compared with contents of the multi-processor register, and a virtual processor field of the TLB is compared with contents of a virtual processor register. If the value coincides with the multi-processor field or if the value does not coincide with the multi-processor field and the value coincides with the virtual processor field, contents of an absolute address field of the TLB are input to an absolute address register. This increases the effective capacity and utilization of the TLB to avoid decreasing of performance of the virtual machines.
Inventors
- 👤 Hiroshi Ikegaya
- 👤 Hidenori Umeno
- 👤 Tsuyoshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 06:06
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1036
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
202 words
An apparatus for translating addresses for virtual machines, comprising: at least one virtual machine of a multi-processor system having a plurality of virtual processors; means for holding a logical address of said virtual machine; a translation lookaside buffer (TLB) for holding a pair of translators for translating the logical address to an absolute address of a real machine, holding a value for indicating whether or not an entry to said TLB corresponds to an area common among said plurality of virtual processors, and storing a value for identifying any of the virtual processors in said multi-processor system; prefix translation means for translating a real address of said at least one virtual machine to an absolute address of said virtual machine; address translation means for translating said logical address to a real address of said at least one virtual machine of said virtual processor; comparison means for comparing a prefix value of any of said virtual processors input according to a system program with the absolute address obtained by said prefix translation means; and means for judging, on the basis of comparison results by said comparison means, whether or not the entry corresponds to the area common among said plurality of virtual processors.
Claim 2
Independent Claim
202 words
An apparatus for translating addresses for virtual machines, comprising: at least one virtual machine of a multi-processor system having a plurality of virtual processors; means for holding a logical address of said virtual machine; a translation lookaside buffer (TLB) for holding a pair of translators for translating the logical address to an absolute address of a real machine, holding a value for indicating whether or not an entry to said TLB corresponds to an area common among said plurality of virtual processors, and storing a value for identifying any of the virtual processors in said multi-processor system; prefix translation means for translating a real address of said at least one virtual machine to an absolute address of said virtual machine; address translation means for translating said logical address to a real address of said at least one virtual machine of said virtual processor; comparison means for comparing a prefix value of any of said virtual processors input according to a system program with the absolute address obtained by said prefix translation means; and means for judging, on the basis of comparison results by said comparison means, whether or not the entry corresponds to the area common among said plurality of virtual processors.
Claim 3
Dependent Claim
29 words
An apparatus according to claim 1, wherein said apparatus includes a plurality of virtual machine, and said TLB further stores a value for identifying any of the virtual machines.
Claim 4
Dependent Claim
28 words
An apparatus according to claim 2, wherein said value for indicating whether or not the entry corresponds to the common area also identifies any of the virtual machines.
Claim 5
Dependent Claim
87 words
An apparatus according to claim 2, further comprising: means for storing a value for identifying a currently running virtual machine and a value for identifying a currently running virtual processor; comparison means for comparing the value for identifying said virtual machine with the value in said TLB for identifying the currently running virtual machine; comparison means for comparing the value for identifying the currently running virtual processor with the value in said TLB for identifying any of the virtual processors; and means for validating the TLB entry.
Claim 6
Dependent Claim
45 words
An apparatus according to claim 1, wherein said TLB has a multi-processor field for storing value for indicating whether or not the entry corresponds to the common area and has a virtual processor field for storing said value for identifying any of the virtual processors.
Claim 7
Dependent Claim
195 words
In a virtual machine system comprising at least one virtual machine of a multi-processor system having a plurality of virtual processors, a method for translating a logical address of said virtual machine to an absolute address of a real machine, said method comprising the steps of: translating the logical address of said virtual machine to the absolute address of said virtual machine by address translation means for translating the logical address of the virtual machine to a real address of the virtual machine and prefix translation means for translating the real address of said virtual machine to the absolute address of said virtual machine; comparing a prefix value for each of said virtual processors input according to a system program with the translated absolute address; inputting, to a translation look-aside buffer (TLB), a value for indicating that an entry corresponds to an area common among said virtual processors if the prefix value and the translated absolute address do not coincide as compared above; and inputting, to the TLB, a value for indicating that the entry is not for the area common among said virtual processors if the prefix value and the translated absolute address coincide.
Claim 8
Dependent Claim
195 words
In a virtual machine system comprising at least one virtual machine of a multi-processor system having a plurality of virtual processors, a method for translating a logical address of said virtual machine to an absolute address of a real machine, said method comprising the steps of: translating the logical address of said virtual machine to the absolute address of said virtual machine by address translation means for translating the logical address of the virtual machine to a real address of the virtual machine and prefix translation means for translating the real address of said virtual machine to the absolute address of said virtual machine; comparing a prefix value for each of said virtual processors input according to a system program with the translated absolute address; inputting, to a translation look-aside buffer (TLB), a value for indicating that an entry corresponds to an area common among said virtual processors if the prefix value and the translated absolute address do not coincide as compared above; and inputting, to the TLB, a value for indicating that the entry is not for the area common among said virtual processors if the prefix value and the translated absolute address coincide.
Claim 9
Dependent Claim
28 words
A method according to claim 6, wherein the value for indicating whether or not the entry corresponds to the common area also identifies any of said virtual processors.
Claim 10
Dependent Claim
38 words
A method according to claim 6, wherein said virtual machine system includes a plurality of virtual machines, and said method further comprises a step for inputting, to the TLB, a value for identifying any of said virtual machines.
Claim 11
Dependent Claim
20 words
A method according to claim 7, wherein the TLB further stores a value for identifying any of said virtual processors.
Claim 12
Dependent Claim
46 words
A method according to claim 9, wherein the TLB has a multi-processor field for storing the value for indicating whether or not the entry corresponds to the common area and has a virtual processor field for storing said value for identifying any of said virtual processors.
Claim 13
Dependent Claim
127 words
A method according to claim 10, further comprising the steps of: comparing a value for identifying a currently running virtual machine with a multi-processor field of the TLB as assigned by a virtual machine control program for controlling said virtual machine system; comparing a value for identifying a currently running virtual processor with a virtual processor field of the TLB as assigned by the control program, and making effective entry to the TLB by determining if the value for identifying said virtual machine coincides with the multi-processor field of the TLB or if the value for identifying said virtual machine does not coincide with the multi-processor field of the TLB and the value for identifying said virtual processor coincides with the virtual processor field of the TLB.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-24 | 1999-01-23 | 1999-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-24 | 2003-01-23 | 2003-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-24 | 2007-01-23 | 2007-07-25 | $7700.00 | Window Closed / Lapsed |