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US5440247A Expired / Lapsed US ⏱️ 0.0 years remaining

Fast CMOS logic with programmable logic control

Assignee: CECIL H KAPLINSKY BYPASS TRUST DATED NOVEMBER 11 1999
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Filing: 1993-05-26
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Granted: 1995-08-08
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Expires: 2013-05-26
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Abstract

Abstract A logic circuit having a programmable first logic circuit stage and a fixed or dedicated combinatorial second logic circuit stage, serving as a macrocell for the first logic circuit stage. At least one input to the logic circuit is connected directly to the second stage, bypassing the first stage. The first stage may be a programmable logic device with a programmable AND plane followed by an OR plane, and is functionally flexible. The second stage has at least two groups of CMOS logic gates arranged in sequence and connected in a fixed manner by hardwiring so as to implement a specified combinatorial logic function that is representable in sum-of-products form, and is fast compared to the first stage. The outputs from the first stage control logic operations of the second stage upon the directly connected input or inputs.

Inventors

  • 👤 Cecil H. Kaplinsky

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 17:50
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 282 words
A two-stage logic circuit comprising a programmable first logic circuit stage having a set of inputs and outputs, said first logic circuit stage being configurable by programming to carry out a specified logic function in response to input signals received by said set of inputs and to provide output signals representing a result of said specified logic function on said outputs of said first logic circuit stage, a fixed combinatorial second logic circuit stage having a first set of inputs connected to at least some of said outputs of said first logic circuit stage, at least one other direct input in a second set of inputs bypassing said first logic circuit stage and connected directly to said second logic circuit stage, and at least one output, said second logic circuit stage including at least two groups of logic gates arranged in sequence and connected together and to said first set of inputs and also to said at least one other input in a fixed manner by hardwiring to implement a specified combinatorial logic function that is representable in sum-of-products form and to provide a result of said function on said at least one output of said second logic circuit stage, wherein said output signals provided on said outputs of said programmable first logic circuit stage to said first set of inputs of said second logic circuit stage control logic operations of said fixed combinatorial second logic circuit stage upon signals received by said at least one other input connected directly to said second logic circuit stage, and wherein said at least one other input of said second logic circuit stage also forms at least one input to said first logic circuit stage.
Claim 2
Dependent Claim 282 words
A two-stage logic circuit comprising a programmable first logic circuit stage having a set of inputs and outputs, said first logic circuit stage being configurable by programming to carry out a specified logic function in response to input signals received by said set of inputs and to provide output signals representing a result of said specified logic function on said outputs of said first logic circuit stage, a fixed combinatorial second logic circuit stage having a first set of inputs connected to at least some of said outputs of said first logic circuit stage, at least one other direct input in a second set of inputs bypassing said first logic circuit stage and connected directly to said second logic circuit stage, and at least one output, said second logic circuit stage including at least two groups of logic gates arranged in sequence and connected together and to said first set of inputs and also to said at least one other input in a fixed manner by hardwiring to implement a specified combinatorial logic function that is representable in sum-of-products form and to provide a result of said function on said at least one output of said second logic circuit stage, wherein said output signals provided on said outputs of said programmable first logic circuit stage to said first set of inputs of said second logic circuit stage control logic operations of said fixed combinatorial second logic circuit stage upon signals received by said at least one other input connected directly to said second logic circuit stage, and wherein said at least one other input of said second logic circuit stage also forms at least one input to said first logic circuit stage.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-08-07 1999-02-06 1999-08-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-08-07 2003-02-06 2003-08-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-08-07 2007-02-06 2007-08-08 $7700.00 Window Closed / Lapsed

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