Clock-generating circuit for clock-controlled logic circuits

Claim 2

In a clock-generating circuit for delivering clock signals to a logic circuit coupled to said clock-generating circuit via clock-signal lines, said logic circuit including decoupling stages which undesirably conduct shunt currents in the absence of said clock signals, the improvement therewith comprising: an interlock circuit adapted to receive at least one input signal, wherein said interlock circuit is coupled to said clock-signal lines and responsive to said at least one input signal, for suspending said delivery of said clock signals and for forcing said clock-signal lines into a state causing said decoupling stages to be placed into a shunt-current-free operating state during the absence of said clock signals.

Claim 3

The clock-generating circuit according to claim 1, wherein said forcing of said clock-signal lines occurs during an interlocking mode controlled by an interlocking signal and wherein said shunt-current-free operating state of said decoupling stages remains stable for the duration of said interlocking mode.

Claim 4

The clock-generating circuit according to claim 2 further including a reset signal generated during a turn-on starting phase wherein said interlocking signal is locked to said reset signal.

Claim 5

The clock-generating circuit according to claim 2 further including a standby signal generated in a standby mode wherein said interlocking signal is locked to said standby signal.

Claim 6

The clock-generating circuit according to claim 2, wherein said interlock circuit includes, for each pair of clock signal lines, at least one gate circuit for combining an input clock signal and said interlocking signal.

Claim 7

The clock-generating circuit according to claim 2, wherein said interlocking circuit includes, for each clock signal line, at least one gate circuit for combining an input clock signal and said interlocking signal.

Claim 8

The clock-generating circuit according to claim 2 further including a synchronizing stage wherein said interlocking signal is provided to said synchronizing stage and said synchronizing stage generates an internal reset signal having a defined turn-off edge synchronized with one of at least one input clock signal, said internal reset signal being provided to said logic circuit.

Claim 9

The clock-generating circuit according to claim 7, wherein said synchronizing stage includes an interference-suppression circuit adapted to receive said interlocking signal for suppressing the effect of any unstable states of said interlocking signal on said logic circuit.

Claim 10

The clock-generating circuit according to claim 8 wherein said unstable states of said interlocking signal are suppressed by means of the synchronization of said turn-off edge of said internal reset signal.

Claim 11

The clock-generating circuit according to claim 8, wherein said synchronizing stage comprises: a clocked delay stage having an input terminal adapted to receive said interlocking signal; a NOR gate having a first input terminal coupled to an output terminal of said delay stage, and having a second input terminal adapted to receive said interlocking signal; a first inverter gate having an input terminal coupled to an output terminal of said NOR gate; a second clocked inverter gate having an input terminal coupled to an output terminal of said first inverter gate; a third clocked inverter gate having an input terminal coupled to an output terminal of said second clocked inverter; a chain of at least one other inverter gate coupled in series between an output terminal of said third clocked inverter and said logic circuit wherein said internal reset signal is generated and provided at an output of said chain of other inverters.

Claim 12

The clock-generating circuit according to claim 10 wherein said clock-generating circuit converts an input clock signal to output clock-signals for said delivering to said logic circuit; said clocked delay stage having a clock input terminal adapted to receive said input clock signal; and wherein said clocked delay stage prolongs logic level 1 signals present at said input terminal of said delay stage by several clock-pulse periods and provides a prolonged logic level 1 signal at said output terminal of said delay stage, and wherein said delay stage suppresses short logic level O input signals.

Claim 13

The clock-generating circuit according to claim 1, wherein said clock-generating circuit generates a nonoverlapping two-phase clock system, said system comprising two pairs of antiphase clock signals wherein said clock signals are provided to said clock-signal lines.

Claim 14

The clock-generating circuit according to claim 2 further comprising: a first inverter gate having an input terminal for receiving an input clock signal; a first AND gate having a first input terminal coupled to an output terminal of said first inverter gate; a second AND gate having a first input terminal coupled to receive said input clock signal; a first NOR gate having a first input terminal coupled to an output terminal of said first AND gate, and having a second input terminal coupled to receive said interlocking signal; a second NOR gate having a first input terminal coupled to an output terminal of said second AND gate, and having a second input terminal coupled to receive said interlocking signal; a first series chain of inverter gates coupled between a first output terminal of said first NOR gate and a first external output clock-signal line wherein a first clock signal is provided to said first output clock-signal line; a second inverter gate having an input terminal coupled to receive said first output clock signal, and having an output terminal, on which a second output clock signal is provided to a second external clock-signal line wherein said output terminal of said second inverter is coupled to a second input terminal of said second AND gate; a second series chain of inverter gates coupled in series between a first output terminal of said second NOR gate and a third external clock-signal line wherein a third output clock signal is provided to said third external clock-signal line; a third inverter gate having an input terminal coupled to receive said third output clock signal, and having an output terminal, on which a fourth output clock signal is provided to a fourth external clock-signal line, and said output terminal of said third inverter gate is coupled to a second input terminal of said first AND gate; whereby a non-overlapping two-phase clock system is generated, said system comprising two pairs of antiphase clock signals provided to said clock signal lines wherein said first and second output clock signals form a first pair of antiphase clock signals and said third and fourth output clock signals form a second pair of said two pairs or antiphase clock signals.

Claim 15

The clock-generating circuit according to claim 3 further comprising a NOR gate and an inverter, wherein said interlocking signal is locked to a standby signal generated in a standby mode, said standby signal being inputted to a first input terminal of said NOR gate, said reset signal being inputted to a second input terminal of said NOR gate, said inverter having an output terminal and having an input terminal coupled to an output terminal of said NOR gate, whereby said interlocking signal is provided at said output terminal of said inverter.

Claim 16

The clock-generating circuit according to claim 14, wherein said reset signal and said standby signal are generated by a controller.

Claim 17

The clock-generating circuit according to claim 1 wherein said decoupling stages comprise clocked inverters adapted to receive said delivered clock signals, each of said clocked inverters including p-channel and n-channel transistors.

Claim 18

The clock-generating circut according to claim 1 wherein each of said decoupling stages comprise a series combination of a nonclocked invertor and a transfer gate.

Claim 19

A clock-generating circuit for logic circuits coupled to said clock-generating circuit by clock-signal lines, for delivering clock signals to said logic circuits, said logic circuits including clock-controlled decoupling stages which undesirably conduct current in the absence of said clock signals, said clock-generating circuit comprising: an interlock circuit adapted to receive at least one input signal, wherein said interlock circuit is coupled to said clock-signal lines and responsive to said at least one input signal for generating an interlocking signal during an interlocking mode; wherein said interlocking circuit is responsive to said interlocking signal to suspend said delivery of said clock signals and to force said clock-signal lines into a first logic level state in which said logic circuits are supplied said first logic level present on said clock-signal lines; wherein said first logic level present on said clock-signal lines causes said decoupling stages to be placed into a shunt-current-free operating state for the duration of said interlocking mode.

Claim 20

A clock-generating circuit for logic circuits coupled to said clock-generating circuit by clock-signal lines, for delivering clock signals to said logic circuits, said logic circuits including clock-controlled decoupling stages which undesirably conduct current in the absence of said clock signals, said clock-generating circuit comprising: an interlock circuit adapted to receive at least one input signal, wherein said interlock circuit is coupled to said clock-signal lines and responsive to said at least one input signal for generating an interlocking signal during an interlocking mode; wherein said interlocking circuit is responsive to said interlocking signal to suspend said delivery of said clock signals and to force said clock-signal lines into a first logic level state in which said logic circuits are supplied said first logic level present on said clock-signal lines; wherein said first logic level present on said clock-signal lines causes said decoupling stages to be placed into a shunt-current-free operating state for the duration of said interlocking mode.

Claim 21

The clock-generating circuit according to claim 18 wherein said delivered clock signals are nonoverlapping two phase clock signals and wherein said clock-generating circuit converts a single input clock signal into said delivered clock signals.

Claim 22

The clock-generating circuit according to claim 18 wherein said interlocking signal is locked to a reset signal, wherein said reset signal is generating by a controller during a turn-on starting phase.