Delay locked loop for detecting the phase difference of two signals having different frequencies

Claim 2

An integrated circuit memory, comprising: a plurality of memory cells, each memory cell coupled to a bit line and to a word line; an output data register, coupled to the plurality of memory cells, the output data register for receiving data signals corresponding to data stored in the plurality of memory cells, the output data register providing an output data signal in response to receiving a delay locked loop signal; and a delay locked loop circuit for receiving a clock signal, and in response, providing the delay locked loop signal, the delay locked loop signal for controlling the output data register.

Claim 3

The integrated circuit memory of claim 1, wherein the delay locked loop circuit comprises: an arbiter circuit for comparing the clock signal to the delay locked loop signal, the clock signal having a first frequency and the delay locked loop signal having a second frequency, and in response, the arbiter circuit providing an retard signal; a control circuit for receiving the retard signal, and in response, providing a control voltage, the control voltage having a magnitude relative to a difference between a transition of the clock signal and a transition of the delay locked loop signal; and a voltage controlled delay circuit, coupled to the control circuit, for receiving the control voltage, and in response, adjusting a phase of the delay locked loop signal with respect to the clock signal.

Claim 4

The integrated circuit memory of claim 2, wherein the arbiter circuit comprises: a first logic gate having a first input terminal for receiving the clock signal, a second input terminal for receiving an enable signal, and an output terminal; a second logic gate having a first input terminal for receiving the delay locked loop signal, a second input terminal for receiving the enable signal, and an output terminal; a third logic gate having a first input terminal coupled to the output terminal of the first logic gate, a second input terminal, and an output terminal; a fourth logic gate having a first input terminal coupled to the output terminal of the second logic gate, a second input terminal coupled to the output terminal of the third logic gate, and an output terminal coupled to the second input terminal of the third logic gate; a first register having an input terminal coupled to the output terminal of the third logic gate, a control terminal for receiving the enable signal, and an output terminal; a second register having an input terminal coupled to the output terminal of the fourth logic gate, and a control terminal for receiving the enable signal; and a third register having an input terminal coupled to the output terminal of the first register, a control terminal for receiving the enable signal, and an output terminal for providing the retard signal.

Claim 5

The integrated circuit memory of claim 3, wherein the first, second, third, and fourth logic gates are each characterized as performing a NAND logic function.

Claim 6

The integrated circuit memory of claim 1, wherein the clock signal and the delay locked loop signal are characterized as being ECL (emitter-coupled logic) signals.

Claim 7

The integrated circuit memory of claim 3, wherein the control circuit comprises: an inverter having an input terminal for receiving the retard signal, and an output terminal for providing the control voltage; a first current source having a first terminal coupled to a first power supply voltage terminal, and a second terminal coupled to the inverter; a second current source having a first terminal coupled to a second power supply voltage terminal, and a second terminal coupled to the inverter; and a capacitor having a first terminal coupled to the output terminal of the inverter, and a second terminal coupled to the first power supply voltage terminal.

Claim 8

The integrated circuit memory of claim 3, wherein the voltage controlled delay circuit comprises: a first differential amplifier having first and second transistors, a first resistive element being coupled between a first power supply voltage terminal and a first current electrode of the first transistor, a second resistive element being coupled between the first power supply voltage terminal and a first current electrode of the second transistor, the first differential amplifier for receiving the enable signal, and an output terminal; a variable current source, coupled to the second current electrodes of the first and second transistors, for receiving the control voltage, and in response, providing a current source for the first differential amplifier proportional to the magnitude of the control voltage; a second differential amplifier having third and fourth transistors, a third resistive element being coupled between the first power supply voltage terminal and a first current electrode of the third transistor, a fourth resistive element being coupled between the first power supply voltage terminal and a first current electrode of the fourth transistor, a control electrode of the third transistor coupled to the first current electrode of the third transistor, and a control electrode of the fourth transistor coupled to the first current electrode of the second transistor; and a latch circuit, coupled to the second differential amplifier, for setting a switching point of the second differential amplifier.

Claim 9

The integrated circuit memory of claim 2, further comprising a collapse detector circuit, the collapse detector circuit for detecting when the delay locked loop signal has not transitioned within a second predetermined time.

Claim 10

The integrated circuit memory of claim 8, wherein the collapse detector circuit comprises: a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a first bias voltage, and a second current electrode; a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode; a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to the control electrode of the second transistor, and a second current electrode coupled to a second power supply voltage terminal; a first capacitive element having a first terminal coupled to the second current electrode of the second transistor, and a second terminal coupled to the second power supply voltage terminal; a logic gate having a first input terminal coupled to the second current electrode of the second transistor, a second input terminal, and an output terminal; a fourth transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode, and a second current electrode coupled to the second input terminal of the logic gate; a fifth transistor having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode coupled to the control electrode of the fourth transistor, and a second current electrode; a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode for receiving a second bias voltage, and a second current electrode coupled to the second power supply voltage terminal; and a second capacitive element having a first terminal coupled to the second current electrode of the fifth transistor, and a second terminal coupled to the first power supply voltage terminal.