Draw processor for a high performance three dimensional graphic accelerator

Claim 2

A draw processor for a graphics accelerator, comprising: geometry pipeline interface circuit coupled to receive a draw packet that contains a set of geometry parameters that define a geometry object including high level screen space descriptions of two dimensional and three dimensional point line and area graphics primitives, the geometry pipeline interface circuit having circuitry that generates a set of adjusted geometry parameters by biasing an x coordinate of each geometry parameter according to an interleave value assigned to the draw processor; rendering circuit coupled to receive the adjusted geometry parameters from the geometry pipeline interface circuit and having circuitry that generates a set of pixels corresponding to the geometry object by performing edgewalking and scan interpolation functions for the adjusted geometry parameters.

Claim 3

The draw processor of claim 1, wherein the geometry pipeline interface circuit generates the adjusted geometry parameters by adding the interleave value to the x coordinate of each geometry parameter.

Claim 4

The draw processor of claim 2, wherein the graphics accelerator includes a frame buffer having N horizontal interleaves, and wherein the interleave value is in a range of 0 through N-1 such that the rendering circuit generates every N th pixel on each of a set of scan lines of a rasterized image corresponding to the geometry object.

Claim 5

The draw processor of claim 3, wherein the frame buffer comprises 5 horizontal interleaves, and wherein the interleave value is in a range of 0 through 4 such that the rendering circuit generates every fifth pixel on each scan line.

Claim 6

The draw processor of claim 1, further comprising a direct port interface circuit coupled to receive a direct port packet that contains a set of pixel function parameters that specify a pixel function of the draw processor from among a set of pixel functions comprising a pixel depth cue function, a write pixel function, and a pixel block copy function.

Claim 7

The draw processor of claim 5, further comprising a memory control circuit coupled to receive the pixels from the rendering circuit and the pixel function parameters from the direct port interface circuit, the memory control circuit having circuitry that writes the pixels into a corresponding interleave portion of a frame buffer while performing the pixel function specified by the pixel function parameters.

Claim 8

A graphics accelerator, comprising a frame buffer having N horizontal interleaves and further comprising a set of N draw processors each coupled to receive a draw packet over a draw bus from a floating-point processor in the graphics accelerator wherein the draw packet contains a set of geometry parameters that define a geometry object including high level screen space descriptions of two dimensional and three dimensional point line and area graphics primitives, each draw processor having a unique assigned interleave value in a range 0 through N-1, each draw processor having circuitry that generates a set of adjusted geometry parameters by biasing an x coordinate of each geometry parameter according to the unique assigned interleave value, each draw processor having circuitry that renders a set of pixels corresponding to the geometry object by performing edgewalking and scan interpolation functions for the adjusted geometry parameters such that each draw processor generates every N th pixel on each of a set of scan lines of a rasterized image corresponding to the geometry object.

Claim 9

A graphics accelerator, comprising a frame buffer having N horizontal interleaves and further comprising a set of N draw processors each coupled to receive a draw packet over a draw bus from a floating-point processor in the graphics accelerator wherein the draw packet contains a set of geometry parameters that define a geometry object including high level screen space descriptions of two dimensional and three dimensional point line and area graphics primitives, each draw processor having a unique assigned interleave value in a range 0 through N-1, each draw processor having circuitry that generates a set of adjusted geometry parameters by biasing an x coordinate of each geometry parameter according to the unique assigned interleave value, each draw processor having circuitry that renders a set of pixels corresponding to the geometry object by performing edgewalking and scan interpolation functions for the adjusted geometry parameters such that each draw processor generates every N th pixel on each of a set of scan lines of a rasterized image corresponding to the geometry object.

Claim 10

The graphics accelerator of claim 7, wherein the frame buffer comprises 5 horizontal interleaves, and wherein each interleave value is in a range of 0 through 4 such that each draw processor renders every fifth pixel on each scan line.

Claim 11

The graphics accelerator of claim 7, wherein each draw processor comprises: geometry pipeline interface circuit coupled to receive the draw packet over the draw bus, the geometry pipeline interface circuit generating the adjusted geometry parameters by biasing the x coordinate of each geometry parameter according to the unique assigned interleave value assigned to the draw processor; rendering circuit coupled to receive the adjusted geometry parameters from the geometry pipeline interface circuit and having circuitry for generating the pixels corresponding to the geometry object by performing edgewalking and scan interpolation functions for the adjusted geometry parameters.

Claim 12

The graphics accelerator of claim 9, wherein each geometry pipeline interface circuit generates the corresponding adjusted geometry parameters by adding the corresponding unique assigned interleave value to the x coordinate of each corresponding geometry parameter.

Claim 13

The graphics accelerator of claim 10, wherein each draw processor further comprises a direct port interface circuit coupled to receive a direct port packet over the draw bus that contains a set of pixel function parameters that specify a pixel function of the draw processor from among a set of pixel functions comprising a pixel depth cue function, a write pixel function, and a pixel block copy function.

Claim 14

The graphics accelerator of claim 11, wherein each draw processor further comprises a memory control circuit coupled to receive the corresponding pixels from the corresponding rendering circuit and the pixel function parameters from the corresponding direct port interface circuit, the memory control circuit having circuitry that writes the corresponding pixels into a corresponding interleave portion of the frame buffer while performing the pixel function specified by the corresponding pixel function parameters.

Claim 17

The method of claim 13, wherein the frame buffer comprises 5 horizontal interleaves, and wherein each unique assigned interleave value is in a range of 0 through 4 such that each horizontal interleave of the frame buffer stores every fifth pixel on each scan line.

Claim 18

The method of claim 13, wherein the step of generating the adjusted geometry parameters for each horizontal interleave comprises the step of adding the corresponding unique assigned interleave value to the x coordinate of each corresponding geometry parameter.

Claim 19

The method of claim 15, further comprising the step of receiving a direct port packet that contains a set of pixel function parameters that specify a pixel function from among a set of pixel functions comprising a pixel depth cue function, a write pixel function, and a pixel block copy function.

Claim 20

The method of claim 16, further comprising the steps writing the pixels into the interleaves of the frame buffer while performing the pixel functions specified by the corresponding pixel function parameters.