Wafer release method and apparatus

Claim 2

A wafer handling method for use in treatment of a semiconductor wafer comprising the steps of: a) placing a semiconductor wafer on a wafer support; b) once the wafer is placed on the wafer support, electrostatically attracting the wafer to the support by electrically biasing the wafer support with a first polarity DC signal to create an electrostatic attraction between the semiconductor wafer and the wafer support; c) treating the wafer while maintaining the electrical bias with the first polarity DC signal to maintain an attraction between the wafer and the wafer support; and d) releasing a treated wafer from the wafer support by applying a second DC polarity signal to the wafer support that is opposite in polarity to the first polarity DC signal, and then applying alternating signals having the first and second polarities at a controlled frequency for a predetermined time interval to reduce the electrostatic attraction between the wafer and the wafer support.

Claim 3

The wafer handling method set forth in claim 1 additionally comprising the step of detecting a presence of a wafer on the wafer support prior to treatment of the wafer.

Claim 4

The wafer handling method set forth in claim 2 wherein the step of detecting a presence of a wafer on the wafer support includes sensing a capacitance between two spaced apart electrodes coupled to the wafer support.

Claim 5

The wafer handling method set forth in claim 1 additionally comprising the step of removing the treated wafer from the wafer support.

Claim 6

Wafer treatment apparatus for supporting a semiconductor wafer comprising: a) a wafer support including a dielectric surface that engages the wafer and two electrodes; b) a power supply for energizing the two electrodes comprising circuitry for providing controlled first and second polarity bias signals across the electrodes; and c) an implantation control system coupled to the power supply including circuitry for securing the wafer to the wafer support during ion implantation by applying one of the first and second polarity bias signals across the electrodes thereby electrostatically attracting the wafer to the wafer support and for releasing the wafer from the wafer support after implantation of the wafer is complete by alternately applying the first and second polarity bias signals to the electrodes at a controlled frequency for a predetermined time interval to reduce the electrostatic attraction of the wafer to the wafer support.

Claim 7

Wafer treatment apparatus for supporting a semiconductor wafer comprising: a) a wafer support including a dielectric surface that engages the wafer and two electrodes; b) a power supply for energizing the two electrodes comprising circuitry for providing controlled first and second polarity bias signals across the electrodes; and c) an implantation control system coupled to the power supply including circuitry for securing the wafer to the wafer support during ion implantation by applying one of the first and second polarity bias signals across the electrodes thereby electrostatically attracting the wafer to the wafer support and for releasing the wafer from the wafer support after implantation of the wafer is complete by alternately applying the first and second polarity bias signals to the electrodes at a controlled frequency for a predetermined time interval to reduce the electrostatic attraction of the wafer to the wafer support.

Claim 8

The apparatus of claim 5 additionally comprising sensor circuitry to sense an attraction between the wafer and the wafer support produced by the power supply based upon sensed capacitance between the electrodes when the power supply energizes the electrodes.

Claim 9

The apparatus of claim 5 wherein the controller comprises an oscillator circuit coupled to the power supply to change the bias on the electrodes at the controlled frequency for a controlled time interval.

Claim 10

The wafer treatment apparatus of claim 5 further including capacitance sense circuitry means for detecting a presence or absence of the wafer on the wafer support by sensing a capacitance between the two electrodes.

Claim 11

The wafer treatment apparatus of claim 8 wherein the capacitance sense circuitry means produces an output signal indicative of the presence of the wafer on the wafer support, the output signal being coupled to the implantation control system such that the electrodes are be energized only when the output signal indicates a wafer is present on the wafer support.

Claim 12

The wafer treatment apparatus of claim 5 wherein the dielectric surface is comprised of alumina.

Claim 13

The wafer treatment apparatus of claim 5 wherein the power supply comprises two supply modules and the implantation control system circuitry includes a logic driver circuit having first and second complementary outputs, each output coupled to a different one of the bi-polar output power supply modules such that when one of the first and second driver outputs is logic high the supply module coupled to the high driver output applies a signal to the electrodes and the other of the first and second driver outputs is logic low, the supply module coupled to the low driver output being disabled.

Claim 14

Apparatus for use in ion implantation of semiconductor wafers comprising: a) a dielectric layer for supporting a semiconductor wafer; b) a base member supporting said dielectric layer; c) first and second electrodes positioned behind said dielectric layer and supported within said base member; d) means for securing the wafer to the dielectric layer by applying a non-pulsing first polarity DC bias signal to said first and second electrodes to create an electrostatic attractive force between said dielectric layer and said wafer; and e) means for sensing a capacitance between the first and second electrodes and monitoring a change in said capacitance as the wafer is placed on the dielectric layer and for further monitoring a change in said capacitance as the wafer is held in place by the electrostatic attractive force between the wafer and the first and second electrodes; and f) means for releasing the wafer from the dielectric layer by applying a second non-pulsing DC polarity that is opposite to the first polarity and then alternating the first and second polarity DC bias signals at a controlled frequency for a predetermined time interval.

Claim 15

Apparatus for use in ion implantation of semiconductor wafers comprising: a) a dielectric layer for supporting a semiconductor wafer; b) a base member supporting said dielectric layer; c) first and second electrodes positioned behind said dielectric layer and supported within said base member; d) means for securing the wafer to the dielectric layer by applying a non-pulsing first polarity DC bias signal to said first and second electrodes to create an electrostatic attractive force between said dielectric layer and said wafer; and e) means for sensing a capacitance between the first and second electrodes and monitoring a change in said capacitance as the wafer is placed on the dielectric layer and for further monitoring a change in said capacitance as the wafer is held in place by the electrostatic attractive force between the wafer and the first and second electrodes; and f) means for releasing the wafer from the dielectric layer by applying a second non-pulsing DC polarity that is opposite to the first polarity and then alternating the first and second polarity DC bias signals at a controlled frequency for a predetermined time interval.

Claim 16

The apparatus of claim 12 additionally comprising a controller for controlling a rate at which the power supply changes the polarity of the bias applied to said electrodes.

Claim 17

The apparatus of claim 13 where the controller comprises an oscillator that switches the polarity at a clock frequency based upon an oscillator frequency.

Claim 18

The apparatus of claim 12 wherein the means for securing the wafer to the dielectric layer comprises two power supply modules coupled together and further comprises a power supply controller for rendering one or the other of said two power supply modules active to control the polarity of the signal across the first and second electrodes.

Claim 19

A wafer handling method for use in treatment of a semiconductor wafer comprising the steps of: a) placing a semiconductor wafer on a wafer support; b) once the wafer is on the wafer support, securing the wafer to the support by enabling one of two power supply modules resulting in a non-pulsing DC waveform of a first polarity being placed across the electrodes; c) treating the wafer while maintaining the attraction between the wafer and the wafer support; and d) removing the wafer from the wafer support by enabling the other of the two power supply modules such that the other module, when activated, places a second polarity across the electrodes that is opposite to the first polarity, and then alternating the first and second polarities at a controlled frequency for a predetermined period of time.

Claim 20

A wafer handling method for use in treatment of a semiconductor wafer comprising the steps of: a) placing a semiconductor wafer on a wafer support; b) once the wafer is on the wafer support, securing the wafer to the support by enabling one of two power supply modules resulting in a non-pulsing DC waveform of a first polarity being placed across the electrodes; c) treating the wafer while maintaining the attraction between the wafer and the wafer support; and d) removing the wafer from the wafer support by enabling the other of the two power supply modules such that the other module, when activated, places a second polarity across the electrodes that is opposite to the first polarity, and then alternating the first and second polarities at a controlled frequency for a predetermined period of time.

Claim 21

Apparatus for use in ion implantation of semiconductor wafers comprising: a) a dielectric layer for supporting a semiconductor wafer; b) a base member supporting said dielectric layer; c) first and second electrodes positioned behind said dielectric layer and supported within said base member; d) power supply means for applying an electric potential to said first and second electrodes to create an electrostatic attractive force between said dielectric layer and said wafer; e) means for sensing capacitance between the first and second electrodes and monitoring a change in said capacitance as the wafer is placed on the dielectric layer and for further monitoring a change in said capacitance as the wafer is held in place by the electrostatic attractive force between the wafer and the first and second electrodes; and f) said power supply means comprising two power supply modules coupled together and further comprising a power supply controller for rendering one of said two power supply modules active to produce a nonpulsing DC waveform of a first polarity across the first and second electrodes to secure the wafer to the dielectric layer, and for rendering the other of said two power supply modules active to place a second polarity across the first and second electrodes that is opposite to the first polarity, and then alternating the first and second polarities at a controlled frequency for a predetermined period of time to release the wafer from the dielectric layer.

Claim 22

Apparatus for use in ion implantation of semiconductor wafers comprising: a) a dielectric layer for supporting a semiconductor wafer; b) a base member supporting said dielectric layer; c) first and second electrodes positioned behind said dielectric layer and supported within said base member; d) power supply means for applying an electric potential to said first and second electrodes to create an electrostatic attractive force between said dielectric layer and said wafer; e) means for sensing capacitance between the first and second electrodes and monitoring a change in said capacitance as the wafer is placed on the dielectric layer and for further monitoring a change in said capacitance as the wafer is held in place by the electrostatic attractive force between the wafer and the first and second electrodes; and f) said power supply means comprising two power supply modules coupled together and further comprising a power supply controller for rendering one of said two power supply modules active to produce a nonpulsing DC waveform of a first polarity across the first and second electrodes to secure the wafer to the dielectric layer, and for rendering the other of said two power supply modules active to place a second polarity across the first and second electrodes that is opposite to the first polarity, and then alternating the first and second polarities at a controlled frequency for a predetermined period of time to release the wafer from the dielectric layer.