Data output equipment for a semiconductor memory device

Claim 2

A data output equipment for a semiconductor memory device comprises: a fuse programmable delay controller to generate a detecting signal det depending on a fuse connection; a data output enable signal generator to generate a data output buffer enable signal OE depending on said detecting signal det and control signals ew, cs, ay, cas and oexm; and a data output buffer to output reading data from a memory cell depending on said data output enable signal OE.

Claim 3

The data output equipment of claim 1, wherein said fuse programmable delay controller comprises; a fuse connected between a supply voltage VCC and a node N2; an inverter G9 connected between said node N2 and a node N3; an inverter G10 connected between said node N2 and a det terminal to output said detecting signal det; a transistor Q1 connected between said node N2 and a ground VSS, with said transistor Q1 having a gate electrode connected to said node N2; and a capacitor cap1 connected between said node N2 and said ground VSS.

Claim 4

The data output equipment of claim 1, wherein said data output enable signal generator comprises: a reading and writing control signal generator to output a logic high signal while said memory cell is in stand-by operation, and to output a logic low signal while said memory cell is in reading operation depending on said control signal ew, cs, ay and cas through an output node N1 connected to an input terminal of NOR gate G15; a time delay circuit having an output node N4 to delay said logic signals from said output node N1 depending on said detecting signal det, with said output node N4 connecting to another input terminal of said NOR gate G15; and a NAND gate G16 having an input terminal connected to an output terminal of said NOR gate 15, another input terminal to receive said control signal oexm and an output terminal connected to a inverter G17 to output said data output buffer enable signal OE.

Claim 5

The data output equipment of claim 3, wherein said time delay circuit comprises an inverter G11 having an input terminal connected to said output node N1 and an output terminal connected to an input terminal of a NOR gate G12, with said NOR gate G12 having another input terminal to receive said detecting signal det and an output terminal connected to an inverter G14 of which an output terminal is connected to said output node N4 via an inverter G13.

Claim 6

A data output equipment for a semiconductor memory device comprises: a bond pad having a VCC voltage source bonding region and a VSS ground bonding region; a data output enable signal generator to generate a data output buffer enable signal OE depending on an logic signal bond of said bond pad and control signals ew, cs, ay, cas and oexm; and a data output buffer to output reading data from a memory cell according to said data output enable signal OE.

Claim 7

A data output equipment for a semiconductor memory device comprises: a bond pad having a VCC voltage source bonding region and a VSS ground bonding region; a data output enable signal generator to generate a data output buffer enable signal OE depending on an logic signal bond of said bond pad and control signals ew, cs, ay, cas and oexm; and a data output buffer to output reading data from a memory cell according to said data output enable signal OE.

Claim 8

The data output equipment of claim 5, wherein said data output enable signal generator comprises: a reading and writing control signal generator to output a logic high signal while said memory cell is in stand-by operation, and to output a logic low signal while said memory cell is in reading operation depending on said control signal ew, cs, ay and cas through an output node N1 connected to an input terminal of NOR gate G15; a time delay circuit having an output node N4 to delay said logic signals from said output node N1 depending on said logic signal bond, with said output node N4 connecting to another input terminal of said NOR gate G15; and a NAND gate G16 having an input terminal connected to an output terminal of said NOR gate 15, another input terminal to receive said control signal oexm and an output terminal connected to a inverter G17 to output said data output buffer enable signal OE.

Claim 9

The data output equipment of claim 6, wherein said time delay circuit comprises an inverter G11 having an input terminal connected to said output terminal N1 and an output terminal connected to an input terminal of a NOR gate G12, with said NOR gate G12 having another input terminal to receive said logic signal bond and an output terminal connected to an inverter G14 of which an output terminal is connected to said output node N4 via an inverter G13.