US5449934A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device and process
Assignee: Panasonic Holdings Corp
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Filing: 1994-04-29
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Granted: 1995-09-12
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Expires: 2014-04-29
Abstract
Abstract A semiconductor memory device with a storage capacitor is provided which accomplishes a large storage capacity together with a high component density, and facilitates the production. A switching transistor is formed locally in a semiconductor substrate. Formed over the transistor is an upper-level wire disposed over which is a storage capacitor. A storage capacitor contact passes through the upper-level wire. While ensuring a good capacity for the storage capacitor contact, the allowance of focus, too, can advantageously be obtained in simultaneously transferring a pattern of the upper-level wire onto the memory cell region as well as onto the peripheral circuit region. Particularly, by having the storage capacitor contact pass through a bit line, a drain and a source can symmetrically be arranged with a word line, like a memory cell with a bit-line-over-storage-capacitor organization cell. This eliminates an excess portion resulting in increasing the density.
Inventors
- 👤 Tomofumi Shono
- 👤 Teruhito Ohnishi
- 👤 Masanori Fukumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:18
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4403; H10W20/4405; H10W20/4407; H10B; H10B12/00; H10B12/30; H10B12/31; H10W20/425; H10W20/4437; H10W20/4441
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
116 words
A semiconductor memory device comprising: a switching transistor that is formed in a semiconductor substrate having an ion diffused layer near a surface of the semiconductor substrate, the ion diffused layer forming a source and a drain of the switching transistor, a bit line that is formed over the switching transistor and is directly coupled to a part of the ion diffused layer of the switching transistor; and a storage capacitor formed over the bit line, said storage capacitor comprising a storage capacitor contact which couples said storage capacitor to the ion diffused layer of the switching transistor, wherein the storage capacitor contact is formed such that the storage capacitor contact passes through the bit line.
Claim 2
Dependent Claim
116 words
A semiconductor memory device comprising: a switching transistor that is formed in a semiconductor substrate having an ion diffused layer near a surface of the semiconductor substrate, the ion diffused layer forming a source and a drain of the switching transistor, a bit line that is formed over the switching transistor and is directly coupled to a part of the ion diffused layer of the switching transistor; and a storage capacitor formed over the bit line, said storage capacitor comprising a storage capacitor contact which couples said storage capacitor to the ion diffused layer of the switching transistor, wherein the storage capacitor contact is formed such that the storage capacitor contact passes through the bit line.
Claim 3
Dependent Claim
147 words
A semiconductor memory device comprising: a switching transistor that is formed in a semiconductor substrate having an ion diffused layer near a surface of the semiconductor substrate, the ion diffused layer forming a source and a drain of the switching transistor; a bit line that is formed over the switching transistor and is directly coupled to a part of the ion diffused layer of the switching transistor; and a storage capacitor formed over the bit line, said storage capacitor comprising a storage capacitor contact which couples said storage capacitor to the ion diffused layer of the switching transistor, wherein the storage capacitor contact is formed such that, at a point where the storage capacitor contact and the bit line cross, only a portion of the storage capacitor contact passes through the bit line, while the remaining portion of the storage capacitor contact passes outside the bit line.
Claim 4
Dependent Claim
147 words
A semiconductor memory device comprising: a switching transistor that is formed in a semiconductor substrate having an ion diffused layer near a surface of the semiconductor substrate, the ion diffused layer forming a source and a drain of the switching transistor; a bit line that is formed over the switching transistor and is directly coupled to a part of the ion diffused layer of the switching transistor; and a storage capacitor formed over the bit line, said storage capacitor comprising a storage capacitor contact which couples said storage capacitor to the ion diffused layer of the switching transistor, wherein the storage capacitor contact is formed such that, at a point where the storage capacitor contact and the bit line cross, only a portion of the storage capacitor contact passes through the bit line, while the remaining portion of the storage capacitor contact passes outside the bit line.
References Cited (Backward Citations)
US4937645A
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JPH02137363A
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JPH03256358A
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JPH03297166A
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US5095346A
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US5365095A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-11 | 1999-03-13 | 1999-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-11 | 2003-03-13 | 2003-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-11 | 2007-03-13 | 2007-09-12 | $7700.00 | Window Closed / Lapsed |