Rule structure for insertion of new elements in a circuit design synthesis procedure

Claim 2

A circuit design synthesis process performed by a data processing system having a memory with rules having an antecedent portion and a consequence portion and circuit model instances stored in the memory, said process comprising the steps, performed by the data processing system, of: determining, by the data processing system, when a predetermined condition in said antecedent portion of a rule associated with a current circuit model instance and stored in said memory is satisfied; and synthesizing a circuit design by implementing, by the data processing system, said consequence portion of said rule stored in said memory when said predetermined condition is present, said consequence rule portion using a form (outputs . . . )=(operation inputs . . . ) when one of a replace, delete, and insert operation is to be performed on said current circuit model instance, and where said outputs and inputs each comprise one of signal names and memory accesses to pins of said current model instance.

Claim 3

The circuit design synthesis process according to claim 1, the consequence rule portion including a command including a nested equation, and the process further comprising the step of performing one of the replace, delete, and insertion operations in accordance with the nested equation in the command.

Claim 4

The synthesis process of claim 1 wherein an equation format contained in said consequence portion includes circuit model instances, port instances and circuit model signals identifiers.

Claim 5

The synthesis process of claim 3 further including the step of storing signed identifiers in a temporary storage location in a said memory of said data processing sytem.

Claim 6

A process performed by a data processing system having a memory for synthesis of a circuit design, the process comprising the steps, performed by the data processing system, of: utilizing, by the data processing system, rules stored in said memory of said data processing system, said rules having an antecedent portion and a consequence portion; and synthesizing a circuit design by inserting, by the data processing system, model instances into a logic design data base stored in said memory of said system according to a rule associated with each current model instance, and connectivity for each model instance having at least one of an input and an output, said inserting being performed in accordance with an equation format contained in said consequence portion, said equation format defining one of input and output signals or memory accesses to pins of each current model instance.

Claim 7

A process performed by a data processing system having a memory for synthesis of a circuit design, the process comprising the steps, performed by the data processing system, of: utilizing, by the data processing system, rules stored in said memory of said data processing system, said rules having an antecedent portion and a consequence portion; and synthesizing a circuit design by inserting, by the data processing system, model instances into a logic design data base stored in said memory of said system according to a rule associated with each current model instance, and connectivity for each model instance having at least one of an input and an output, said inserting being performed in accordance with an equation format contained in said consequence portion, said equation format defining one of input and output signals or memory accesses to pins of each current model instance.

Claim 8

A data processing system for performing a circuit design synthesis process, the data processing system having a memory, with rules having an antecedent portion and a consequence portion and circuit model instances stored in the memory, the system including: means for determining when a predetermined condition in said antecedent portion of a rule associated with a current circuit model instance and stored in said memory is satisfied; and means for synthesizing a circuit design by implementing said consequence portion of said rule stored in said memory when said predetermined condition is present, said consequence rule portion using a form (outputs . . . )=(operation inputs . . . ) when one of a replace, delete, and insert operation is to be performed on said current circuit model instance, and where said outputs and inputs each comprise one of signal names and memory accesses to pins of said current model instance.

Claim 9

A data processing system for performing a circuit design synthesis process, the data processing system having a memory, with rules having an antecedent portion and a consequence portion and circuit model instances stored in the memory, the system including: means for determining when a predetermined condition in said antecedent portion of a rule associated with a current circuit model instance and stored in said memory is satisfied; and means for synthesizing a circuit design by implementing said consequence portion of said rule stored in said memory when said predetermined condition is present, said consequence rule portion using a form (outputs . . . )=(operation inputs . . . ) when one of a replace, delete, and insert operation is to be performed on said current circuit model instance, and where said outputs and inputs each comprise one of signal names and memory accesses to pins of said current model instance.

Claim 10

The system of claim 6, wherein an equation format contained in said consequence portion includes circuit model instances, port instances, and circuit model signal identifiers.

Claim 11

The system of claim 7, further including means for storing signed identifiers in a temporary storage location in said memory of said data processing system.

Claim 12

The system according to claim 6, the consequence rule portion including a command including a nested equation, and the system further comprising means for performing one of the replace, delete, and insertion operations in accordance with the nested equation in the command.

Claim 13

A data processing system, for performing synthesis of a circuit design, having a memory, the system comprising: means for utilizing rules stored in said memory of said data processing system, said rules having an antecedent portion and a consequence portion; and means for synthesizing a circuit design by inserting model instances into a logic design data base stored in said memory of said system according to a rule associated with each current model instance, and connectivity for each model instance having at least one of an input and an output, said synthesizing means inserting the model instances in accordance with an equation format contained in said consequence portion, said equation format defining one of input and output signals or memory accesses to pins of each current model instance.

Claim 14

A data processing system, for performing synthesis of a circuit design, having a memory, the system comprising: means for utilizing rules stored in said memory of said data processing system, said rules having an antecedent portion and a consequence portion; and means for synthesizing a circuit design by inserting model instances into a logic design data base stored in said memory of said system according to a rule associated with each current model instance, and connectivity for each model instance having at least one of an input and an output, said synthesizing means inserting the model instances in accordance with an equation format contained in said consequence portion, said equation format defining one of input and output signals or memory accesses to pins of each current model instance.

Claim 15

A circuit design synthesis process performed by a data processing system having a memory in which a plurality of rules and a circuit representation including a plurality of interconnected model instances are stored, each of the rules having an antecedent portion and a consequence portion which contains a command, the process comprising the steps, performed by the data processing system, of: determining, by the data processing system, whether the antecedent portion of a first one of the plurality of rules is true with respect to a first one of the plurality of model instances; implementing, by the data processing system, when the antecedent portion of the first rule is determined to be true, the command in the consequence portion of the first rule by determining a boundary of a first subset of the circuit representation and replacing the first subset with a second subset to perform synthesis of a circuit design, the boundary of the first subset being identified by the command in the consequence portion of the first rule.

Claim 16

A circuit design synthesis process performed by a data processing system having a memory in which a plurality of rules and a circuit representation including a plurality of interconnected model instances are stored, each of the rules having an antecedent portion and a consequence portion which contains a command, the process comprising the steps, performed by the data processing system, of: determining, by the data processing system, whether the antecedent portion of a first one of the plurality of rules is true with respect to a first one of the plurality of model instances; implementing, by the data processing system, when the antecedent portion of the first rule is determined to be true, the command in the consequence portion of the first rule by determining a boundary of a first subset of the circuit representation and replacing the first subset with a second subset to perform synthesis of a circuit design, the boundary of the first subset being identified by the command in the consequence portion of the first rule.

Claim 17

The process according to claim 11, wherein the boundary of the first subset includes a plurality of port instances.

Claim 18

The process according to claim 11, wherein the command in the consequence portion of the first rule further identifies a boundary of the second subset and model instances included in the first and second subsets.

Claim 19

The process according to claim 11, wherein the first subset includes a plurality of model instances and the second subset includes only a single model instance.

Claim 20

The process according to claim 11, wherein the first subset includes only a single model instance and the second subset includes a plurality of model instances.

Claim 21

The process according to claim 11, wherein the first subset includes only a single model instance and the second subset includes only a single model instance.

Claim 22

The process according to claim 11, wherein the first subset includes a plurality of model instances and the second subset includes a plurality of model instances.

Claim 23

A data processing system for performing a circuit design synthesis process, the data processing system having a memory in which a plurality of rules and a circuit representation including a plurality of interconnected model instances are stored, each of the rules having an antecedent portion and a consequence portion which contains a command, the system comprising: means for determining whether the antecedent portion of a first one of the plurality of rules is true with respect to a first one of the plurality of model instances; means for implementing, when the antecedent portion of the first rule is determined to be true, the command in the consequence portion of the first rule by determining a boundary of a first subset of the circuit representation and replacing the first subset with a second subset to perform synthesis of a circuit design, the boundary of the first subset being identified by the command in the consequence portion of the first rule.

Claim 24

A data processing system for performing a circuit design synthesis process, the data processing system having a memory in which a plurality of rules and a circuit representation including a plurality of interconnected model instances are stored, each of the rules having an antecedent portion and a consequence portion which contains a command, the system comprising: means for determining whether the antecedent portion of a first one of the plurality of rules is true with respect to a first one of the plurality of model instances; means for implementing, when the antecedent portion of the first rule is determined to be true, the command in the consequence portion of the first rule by determining a boundary of a first subset of the circuit representation and replacing the first subset with a second subset to perform synthesis of a circuit design, the boundary of the first subset being identified by the command in the consequence portion of the first rule.

Claim 25

The process according to claim 18, wherein the boundary of the first subset includes a plurality of port instances.

Claim 26

The system according to claim 18, wherein the command in the consequence portion of the first rule further identifies a boundary of the second subset and model instances included in the first and second subsets.

Claim 27

The system according to claim 18, wherein the first subset includes a plurality of model instances and the second subset includes only a single model instance.

Claim 28

The process according to claim 18, wherein the first subset includes only a single model instance and the second subset includes a plurality of model instances.

Claim 29

The process according to claim 18, wherein the first subset includes only a single model instance and the second subset includes only a single model instance.

Claim 30

The process according to claim 18, wherein the first subset includes a plurality of model instances and the second subset includes a plurality of model instances.

Claim 31

In a data processing system for performing a circuit design synthesis process, the data processing system having a memory in which a plurality of rules, and a circuit representation including a plurality of model instances and a plurality of signal representations, are stored, each of the rules having an antecedent portion and a consequence portion, a method comprising the steps, performed by the data processing system, of: analyzing, by the data processing system, whether the consequence portion of a selected one of the plurality of rules includes an expression that includes a signal representation name, and when the expression does include a signal representation name, determining whether the signal representation name is local to the selected rule; appending, by the data processing system, a substring to the signal representation name, when the signal representation name is local to the selected rule, in order to form a modified signal representation name, the substring being unique to the selected rule; and accessing, by the data processing system, a signal representation stored in the memory that corresponds to the modified signal representation name in accordance with the expression in the consequence portion of the selected rule to perform synthesis of a circuit design.

Claim 32

In a data processing system for performing a circuit design synthesis process, the data processing system having a memory in which a plurality of rules, and a circuit representation including a plurality of model instances and a plurality of signal representations, are stored, each of the rules having an antecedent portion and a consequence portion, a method comprising the steps, performed by the data processing system, of: analyzing, by the data processing system, whether the consequence portion of a selected one of the plurality of rules includes an expression that includes a signal representation name, and when the expression does include a signal representation name, determining whether the signal representation name is local to the selected rule; appending, by the data processing system, a substring to the signal representation name, when the signal representation name is local to the selected rule, in order to form a modified signal representation name, the substring being unique to the selected rule; and accessing, by the data processing system, a signal representation stored in the memory that corresponds to the modified signal representation name in accordance with the expression in the consequence portion of the selected rule to perform synthesis of a circuit design.

Claim 33

The method according to claim 25, wherein the signal representation is a bit signal representation representing a bit in a multi-bit signal, and the bit signal representation is identified by a term in the expression.

Claim 34

The method according to claim 25, wherein the accessing step includes: looking up the modified signal representation name in a signal table stored in the memory in order to determine whether the modified signal representation name exists in the signal table; accessing, when the modified signal representation name exists in the signal table, the signal representation stored in the memory that corresponds to the modified signal representation name.

Claim 35

The method according to claim 25, wherein the accessing step includes: looking up the modified signal representation name in a signal table stored in the memory in order to determine whether the modified signal representation name exists in the signal table; creating, when the modified signal representation name does not exist in the signal table, a new signal name, placing the new signal name in the signal table, and accessing the signal representation stored in the memory that corresponds to the new signal name.

Claim 36

The method according to claim 25, the circuit representation further including a plurality of port instances, and the method further comprising the step of: indirectly accessing the signal representation stored in the memory, when the expression for accessing the signal representation does not include a signal representation name, by way of a port instance identified by the expression.

Claim 37

A data processing system for performing a circuit design synthesis process and a signal representation access method used in the performing of the circuit design synthesis process, the data processing system having a memory in which a plurality of rules, and a circuit representation including a plurality of model instances and a plurality of signal representations, are stored, each of the rules having an antecedent portion and a consequence portion, the system comprising: means for analyzing whether the consequence portion of a selected one of the plurality of rules includes an expression that includes a signal representation name, and when the expression does include a signal representation name, determining whether the signal representation name is local to the selected rule; means for appending a substring to the signal representation name, when the signal representation name is local to the selected rule, in order to form a modified signal representation name, the substring being unique to the selected rule; and means for accessing a signal representation stored in the memory that corresponds to the modified signal representation name in accordance with the expression in the consequence portion of the selected rule to perform synthesis of a circuit design.

Claim 38

A data processing system for performing a circuit design synthesis process and a signal representation access method used in the performing of the circuit design synthesis process, the data processing system having a memory in which a plurality of rules, and a circuit representation including a plurality of model instances and a plurality of signal representations, are stored, each of the rules having an antecedent portion and a consequence portion, the system comprising: means for analyzing whether the consequence portion of a selected one of the plurality of rules includes an expression that includes a signal representation name, and when the expression does include a signal representation name, determining whether the signal representation name is local to the selected rule; means for appending a substring to the signal representation name, when the signal representation name is local to the selected rule, in order to form a modified signal representation name, the substring being unique to the selected rule; and means for accessing a signal representation stored in the memory that corresponds to the modified signal representation name in accordance with the expression in the consequence portion of the selected rule to perform synthesis of a circuit design.

Claim 39

The method according to claim 30, wherein the signal representation is a bit signal representation representing a bit in a multi-bit signal, and the bit signal representation is identified by a term in the expression.

Claim 40

The system according to claim 30, wherein the accessing means includes: means for looking up the modified signal representation name in a signal table stored in the memory in order to determine whether the modified signal representation name exists in the signal table; means for accessing, when the modified signal representation name exists in the signal table, the signal representation stored in the memory that corresponds to the modified signal representation name.

Claim 41

The method according to claim 30, wherein the accessing means includes: means for looking up the modified signal representation name in a signal table stored in the memory in order to determine whether the modified signal representation name exists in the signal table; means for creating, when the modified signal representation name does not exist in the signal table, a new signal name, placing the new signal name in the signal table, and accessing the signal representation stored in the memory that corresponds to the new signal name.

Claim 42

The system according to claim 30, the circuit representation further including a plurality of port instances, and the system further comprising: means for indirectly accessing the signal representation stored in the memory, when the expression for accessing the signal representation does not include a signal representation name, by way of a port instance identified by the expression.

Claim 43

In a data processing system performing a circuit design synthesis process, the data processing system having a memory in which a circuit representation including a plurality of model instances and a plurality of signal representations is stored, a method of generating a plurality of executable rules, from a plurality of source rules, to be used for modifying the circuit representation, the method comprising the steps, performed by the data processing system, of: determining, by the data processing system, when a name contained in a source rule inputted to the data processing system is a signal representation name, whether the signal representation name is local to the source rule; generating, by the data processing system, when the signal representation name is local to the source rule, an expression contained within the executable rule, the expression being used for accessing a signal representation stored in the memory that corresponds to the signal representation name to perform synthesis of a circuit design and including an instruction for appending a substring, unique to the rule, to the signal representation name in order to form a modified signal representation name.

Claim 44

In a data processing system performing a circuit design synthesis process, the data processing system having a memory in which a circuit representation including a plurality of model instances and a plurality of signal representations is stored, a method of generating a plurality of executable rules, from a plurality of source rules, to be used for modifying the circuit representation, the method comprising the steps, performed by the data processing system, of: determining, by the data processing system, when a name contained in a source rule inputted to the data processing system is a signal representation name, whether the signal representation name is local to the source rule; generating, by the data processing system, when the signal representation name is local to the source rule, an expression contained within the executable rule, the expression being used for accessing a signal representation stored in the memory that corresponds to the signal representation name to perform synthesis of a circuit design and including an instruction for appending a substring, unique to the rule, to the signal representation name in order to form a modified signal representation name.

Claim 45

The method according to claim 35, further comprising the step of: generating, when the signal representation is not local to the rule, an expression contained within the executable rule, the expression being used for accessing a signal representation stored in the memory that corresponds to the signal representation name, but not including the substring appending instruction.

Claim 46

The method according to claim 35, wherein the accessing of the signal representation includes: looking up the modified signal representation name in a signal table stored in the memory in order to determine whether the modified signal representation name exists in the signal table; accessing, when the modified signal representation name exists in the signal table, the signal representation stored in the memory that corresponds to the modified signal representation name.

Claim 47

The method according to claim 35, wherein the accessing of the signal representation includes: looking up the modified signal representation name in a signal table stored in the memory in order to determine whether the modified signal representation name exists in the signal table; creating, when the modified signal representation name does not exist in the signal table, a new signal name, placing the new signal name in the signal table, and accessing the signal representation stored in the memory that corresponds to the new signal name.

Claim 48

The method according to claim 35, the circuit representation further including a plurality of port instances, and the method further comprising the step of: generating, when the source rule inputted to the data processing system does not contain a signal representation name, an expression in the executable rule for indirectly accessing a signal representation stored in the memory by way of a port instance identified by the expression.

Claim 49

The method according to claim 35, wherein the signal representation is a bit signal representation representing a bit in a multi-bit signal, and the bit signal representation is identified by a term in the expression.

Claim 50

A data processing system for performing a circuit design synthesis process and for generating a plurality of executable rules, from a plurality of source rules, to be used for modifying a circuit representation stored in a memory of the data processing system, the circuit representation including a plurality of model instances and a plurality of signal representations, the system comprising: means for determining, when a name contained in a source rule inputted to the data processing system is a signal representation name, whether the signal representation name is local to the source rule; means for generating, when the signal representation name is local to the source rule, an expression contained within the executable rule, the expression being used for accessing a signal representation stored in the memory that corresponds to the signal representation name to perform synthesis of a circuit design and including an instruction for appending a substring, unique to the rule, to the signal representation name in order to form a modified signal representation name.

Claim 51

A data processing system for performing a circuit design synthesis process and for generating a plurality of executable rules, from a plurality of source rules, to be used for modifying a circuit representation stored in a memory of the data processing system, the circuit representation including a plurality of model instances and a plurality of signal representations, the system comprising: means for determining, when a name contained in a source rule inputted to the data processing system is a signal representation name, whether the signal representation name is local to the source rule; means for generating, when the signal representation name is local to the source rule, an expression contained within the executable rule, the expression being used for accessing a signal representation stored in the memory that corresponds to the signal representation name to perform synthesis of a circuit design and including an instruction for appending a substring, unique to the rule, to the signal representation name in order to form a modified signal representation name.

Claim 52

The method according to claim 41, further comprising: means for generating, when the signal representation is not local to the rule, an expression contained within the executable rule, the expression being used for accessing a signal representation stored in the memory that corresponds to the signal representation name, but not including the substring appending instruction.

Claim 53

The system according to claim 41, wherein the accessing of the signal representation includes: looking up the modified signal representation name in a signal table stored in the memory in order to determine whether the modified signal representation name exists in the signal table; accessing, when the modified signal representation name exists in the signal table, the signal representation stored in the memory that corresponds to the modified signal representation name.

Claim 54

The system according to claim 41, wherein the accessing of the signal representation includes: looking up the modified signal representation name in a signal table stored in the memory in order to determine whether the modified signal representation name exists in the signal table; creating, when the modified signal representation name does not exist in the signal table, a new signal name, placing the new signal name in the signal table, and accessing the signal representation stored in the memory that corresponds to the new signal name.

Claim 55

The system according to claim 41, the circuit representation further including a plurality of port instances, and the system further comprising: means for generating, when the source rule inputted to the data processing system does not contain a signal representation name, an expression in the executable rule for indirectly accessing a signal representation stored in the memory by way of a port instance identified by the expression.

Claim 56

The system according to claim 41, wherein the signal representation is a bit signal representation representing a bit in a multi-bit signal, and the bit signal representation is identified by a term in the expression.