US5452257A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Address range bank decoding for DRAM
Assignee: Davicom Semiconductor Inc
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Filing: 1994-09-08
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Granted: 1995-09-19
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Expires: 2014-09-08
Abstract
Abstract A method of decoding a memory bank in a DRAM controller system is described that includes obtaining an access address of the bank, defining a begin address of the bank, defining an end address of the bank, and comparing the begin and the end addresses with the access address. A DRAM controller system bank decoding circuit is also disclosed comprising a first comparator for the access address of the bank and the end address of the bank, with an output of the first comparator, corresponding to the access address being less than the end address, connected to a first input of an AND logic gate, a second comparator comparing the access address with the begin address of the bank, with an output of the second comparator, corresponding to the access address being larger than or equal to the begin address, connected to a second input of an AND logic gate.
Inventors
- 👤 Wen C. Han
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:33
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
158 words
A method of a specific DRAM bank address decoding in a DRAM controller system for a DRAM consisted of banks, each of said banks being characterized by a begin address and an end address thereof, said end address of each of said banks, except for a last bank, coinciding with said begin address of an upper-adjacent bank of said banks so that a size of each of said banks is characterized by a difference between said end address and said begin address thereof, said method comprising the steps of: obtaining an access address of said specific bank, defining a begin address of said specific bank, defining an end address of said specific bank, comparing said begin and said end addresses with said access address, and deciding that said access address belongs to said specific bank when said begin address is equal to or less than said access address and said end address is larger than said access address.
Claim 2
Independent Claim
158 words
A method of a specific DRAM bank address decoding in a DRAM controller system for a DRAM consisted of banks, each of said banks being characterized by a begin address and an end address thereof, said end address of each of said banks, except for a last bank, coinciding with said begin address of an upper-adjacent bank of said banks so that a size of each of said banks is characterized by a difference between said end address and said begin address thereof, said method comprising the steps of: obtaining an access address of said specific bank, defining a begin address of said specific bank, defining an end address of said specific bank, comparing said begin and said end addresses with said access address, and deciding that said access address belongs to said specific bank when said begin address is equal to or less than said access address and said end address is larger than said access address.
Claim 3
Dependent Claim
27 words
The method according to claim 1, wherein said defining said begin address of said specific bank comprises adding bank sizes of all banks preceding said specific bank.
Claim 4
Dependent Claim
212 words
A DRAM controller system bank decoding circuit for a DRAM consisted of banks, each of said banks being characterized by a begin address and an end address thereof, said end address of each of said banks, except for a last bank, coinciding with said begin address of an upper-adjacent bank of said banks so that a size of each of said banks is characterized by a difference between said end address and said begin address thereof, said decoding circuit comprising a first comparing means for a first comparison of an access address of a bank of said DRAM with an end address of said bank, an output of said first comparing means corresponding to the result of said first comparison when said access address is less than said end address being assigned a real status, a second comparing means for a second comparison of said access address with a begin address of said bank, an output of said second comparing means corresponding to the result of said second comparison when said access address is equal to or larger than said begin address being assigned a real status, and an AND logic means with inputs thereof being fed from said outputs of said first and said second comparing means having said real status.
Claim 5
Dependent Claim
212 words
A DRAM controller system bank decoding circuit for a DRAM consisted of banks, each of said banks being characterized by a begin address and an end address thereof, said end address of each of said banks, except for a last bank, coinciding with said begin address of an upper-adjacent bank of said banks so that a size of each of said banks is characterized by a difference between said end address and said begin address thereof, said decoding circuit comprising a first comparing means for a first comparison of an access address of a bank of said DRAM with an end address of said bank, an output of said first comparing means corresponding to the result of said first comparison when said access address is less than said end address being assigned a real status, a second comparing means for a second comparison of said access address with a begin address of said bank, an output of said second comparing means corresponding to the result of said second comparison when said access address is equal to or larger than said begin address being assigned a real status, and an AND logic means with inputs thereof being fed from said outputs of said first and said second comparing means having said real status.
References Cited (Backward Citations)
US5134589A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |