Apparatus for converting encoded data into image data, including data preparing circuit, to allow enlargement or reduction of image

Claim 1

An image processing apparatus for decoding encoded data so as to output continuous image data, the apparatus comprising: a) first transforming means for transforming the encoded data into first processing blocks of discrete cosine transformation (DCT) coefficient data, each first processing block including a matrix of m×n pixels; b) setting means for setting values of M and N; c) a data preparing circuit including: 1) means for adding DCT coefficient data having the value of 0 to, or for deleting DCT coefficient data having the value of 0 from, a high-frequency domain of the DCT coefficient data from the first transforming means; and 2) means for preparing second processing blocks of DCT coefficient data, each second processing block including a matrix of M×N pixels; wherein the adding and preparing means collectively include: A) a first register for receiving and storing the value of M; B) a second register for receiving and storing the value of N; C) a first counter for counting a number of lines of DCT coefficient data output from a shift register; D) a second counter for counting a number of bits of DCT coefficient data output from the shift register; E) a first comparator for comparing a count of the first counter with the values of M and m, and for outputting a high-level selection signal, or a read stop signal and a counter reset signal, depending on a first result of comparison; F) a second comparator for comparing a count of the second counter with the values of N and n, and for outputting a high-level selection signal, or a read stop signal and a control signal, depending on a second result of comparison; G) a load signal generating circuit for outputting a load signal to the first and second counters and to the shift register, upon receipt of the control signal from the second comparator; H) the shift register for receiving a parallel data signal via a selector and for outputting the same data signal serially as the image data in the second blocks of M×N pixels, in synchronization with a clock signal output from a clock signal generating circuit; I) the selector for receiving DCT coefficient data in the first processing blocks of m×n pixel matrices, and including means for reading and outputting the same DCT coefficient data when the selection signal input from the first or second comparator is at a low level, and for stopping reading the DCT coefficient data and for outputting a zero signal when the selection signal is at a high level; and J) the clock signal generator for generating the clock signal used by the shift register and the first and second counters; d) second transforming means for subjecting the DCT coefficient data in the second processing blocks to inverse discrete cosine transformation, to provide image data; and e) outputting means for outputting the image data as the continuous image data.