US5454085A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for an enhanced computer system interface
Assignee: EMC Corp
•
Filing: 1995-02-24
•
Granted: 1995-09-26
•
Expires: 2015-02-24
Abstract
Abstract An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.
Inventors
- 👤 Kumar Gajjar
- 👤 Kaushik S. Shah
- 👤 Duc H. Trang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:33
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4213; G06F13/4221; G06F13/4226; G06F3/0668; G06F3/0671; G06F3/0673
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
343 words
A system for transferring digital information including message, status, or command information between an external bus and a device that includes a microprocessor for controlling the transfers of the digital information, the external bus including a first byte-wide group of data lines and a plurality of additional byte-wide groups of data lines which carry the digital information, the external bus further including control signal lines which carry control signals that define operating phases of the external bus in accordance with a Small Computer System Interface (SCSI) communication protocol, the system comprising: a main communication and bus control circuit coupled to the control signal lines and to the first byte-wide group of the data lines, the main communication and bus control circuit including integrated circuitry for generating and receiving the control signals on the control signal lines and for transferring a first byte of the digital information between the first byte-wide group of data lines and the device; a plurality of modular interface extension circuits each coupled to a common one of the control signal lines and each coupled to a dedicated one of the additional byte-wide groups of data lines, each modular interface extension circuit including circuitry for transferring an additional byte of the digital information between its respective byte-wide group of data lines and the device, the transfers of the first and the additional bytes of the digital information being synchronized by a signal from the external bus on the common control signal line; circuitry for transferring the first byte of the digital information between the main communication and bus control circuit and the device; circuitry for transferring the additional bytes of the digital information between the plurality of modular interface extension circuits and the device; and a sequential logic circuit for controlling, in accordance with instructions from the microprocessor, parallel transfer of the first and the additional bytes of the digital information between the external bus and the device when the sequential logic circuit receives a signal from the microprocessor indicating that the digital information is message, status, or command information.
Claim 2
Independent Claim
343 words
A system for transferring digital information including message, status, or command information between an external bus and a device that includes a microprocessor for controlling the transfers of the digital information, the external bus including a first byte-wide group of data lines and a plurality of additional byte-wide groups of data lines which carry the digital information, the external bus further including control signal lines which carry control signals that define operating phases of the external bus in accordance with a Small Computer System Interface (SCSI) communication protocol, the system comprising: a main communication and bus control circuit coupled to the control signal lines and to the first byte-wide group of the data lines, the main communication and bus control circuit including integrated circuitry for generating and receiving the control signals on the control signal lines and for transferring a first byte of the digital information between the first byte-wide group of data lines and the device; a plurality of modular interface extension circuits each coupled to a common one of the control signal lines and each coupled to a dedicated one of the additional byte-wide groups of data lines, each modular interface extension circuit including circuitry for transferring an additional byte of the digital information between its respective byte-wide group of data lines and the device, the transfers of the first and the additional bytes of the digital information being synchronized by a signal from the external bus on the common control signal line; circuitry for transferring the first byte of the digital information between the main communication and bus control circuit and the device; circuitry for transferring the additional bytes of the digital information between the plurality of modular interface extension circuits and the device; and a sequential logic circuit for controlling, in accordance with instructions from the microprocessor, parallel transfer of the first and the additional bytes of the digital information between the external bus and the device when the sequential logic circuit receives a signal from the microprocessor indicating that the digital information is message, status, or command information.
Claim 3
Dependent Claim
52 words
The system of claim 1, wherein the main communication and bus control circuit comprises a bi-directional SCSI bus interface integrated circuit that generates and receives the control signals including the signal on the common control signal line which synchronizes the transfers of the first and the additional bytes of the digital information.
Claim 4
Dependent Claim
32 words
The system of claim 2, wherein the bi-directional SCSI bus interface integrated circuit comprises a first-in, first-out storage circuit which provides the circuitry for transferring the first byte of the digital information.
Claim 5
Dependent Claim
22 words
The system of claim 1, wherein each of the plurality of modular interface extension circuits comprises a bi-directional, first-in, first-out storage circuit.
Claim 6
Dependent Claim
380 words
A mass data storage system for interfacing with a microprocessor, comprising: a mass storage device set; array controller means, coupled to the mass storage device set, for controlling transfers of mass storage data to and from the mass storage device set; device controller means for initiating transfers of digital information including message, status, or command information between the device controller means and the array controller means; a multi-conductor mass storage data communication bus for transferring the digital information between the array controller means and the device controller means, the communication bus having a first byte-wide group of data lines and a plurality of additional byte-wide group of data lines which carry the digital information, and control signal lines which carry control signals that define operating phases of the communication bus in accordance with a Small Computer System Interface-2 (SCSI-2) communication protocol; and interface means, associated with the array controller means and associated with the device controller means, for connecting the array controller means and the device controller means to the communication bus, the interface means comprising: a main communication and bus control circuit coupled to the control signal lines and to the first byte-wide group of the data lines, the main communication and bus control circuit including integrated circuitry for generating and receiving the control signals on the control signal lines and for transferring a first byte of the digital information between the first byte-wide group of data lines and the interface means; a plurality of modular interface extension circuits each coupled to a common one of the control signal lines and each coupled to a dedicated one of the additional byte-wide groups of data lines, each modular interface extension circuit including circuitry for transferring an additional byte of the digital information between its respective byte-wide group of data lines and the interface means, the transfers of the first and additional bytes of the digital information being synchronized by a signal from the external bus on the common control signal line; and sequential logic means for controlling parallel transfer of the first and the additional bytes of the digital information between the external bus and the interface means when the sequential logic means receives a signal from the microprocessor indicating that the digital information is message, status, or command information.
Claim 7
Dependent Claim
380 words
A mass data storage system for interfacing with a microprocessor, comprising: a mass storage device set; array controller means, coupled to the mass storage device set, for controlling transfers of mass storage data to and from the mass storage device set; device controller means for initiating transfers of digital information including message, status, or command information between the device controller means and the array controller means; a multi-conductor mass storage data communication bus for transferring the digital information between the array controller means and the device controller means, the communication bus having a first byte-wide group of data lines and a plurality of additional byte-wide group of data lines which carry the digital information, and control signal lines which carry control signals that define operating phases of the communication bus in accordance with a Small Computer System Interface-2 (SCSI-2) communication protocol; and interface means, associated with the array controller means and associated with the device controller means, for connecting the array controller means and the device controller means to the communication bus, the interface means comprising: a main communication and bus control circuit coupled to the control signal lines and to the first byte-wide group of the data lines, the main communication and bus control circuit including integrated circuitry for generating and receiving the control signals on the control signal lines and for transferring a first byte of the digital information between the first byte-wide group of data lines and the interface means; a plurality of modular interface extension circuits each coupled to a common one of the control signal lines and each coupled to a dedicated one of the additional byte-wide groups of data lines, each modular interface extension circuit including circuitry for transferring an additional byte of the digital information between its respective byte-wide group of data lines and the interface means, the transfers of the first and additional bytes of the digital information being synchronized by a signal from the external bus on the common control signal line; and sequential logic means for controlling parallel transfer of the first and the additional bytes of the digital information between the external bus and the interface means when the sequential logic means receives a signal from the microprocessor indicating that the digital information is message, status, or command information.
Claim 8
Dependent Claim
55 words
The mass data storage system of claim 5, wherein the main communication and bus control circuit comprises a bi-directional SCSI bus interface integrated circuit that generates and receives the control signals including the signal on the common control signal line which synchronizes the transfers of the first and the additional bytes of the digital information.
Claim 9
Dependent Claim
35 words
The mass data storage system of claim 6, wherein the bi-directional SCSI bus interface integrated circuit comprises a first-in, first-out storage circuit which provides the circuitry for transferring the first byte of the digital information.
Claim 10
Dependent Claim
25 words
The mass data storage system of claim 5, wherein each of the plurality of modular interface extension circuits comprises a bi-directional, first-in, first-out storage circuit.
Claim 11
Independent Claim
331 words
A system for transferring digital information including message, status, or command information between an external bus and a device that includes a microprocessor for controlling the transfers of the digital information, the external bus including a first byte-wide group of data lines and a plurality of additional byte-wide groups of data lines which carry the digital information, the external bus further including control signal lines which carry control signals that define operating phases of the external bus, the system comprising: a main communication and bus control circuit coupled to the control signal lines and to the first byte-wide group of the data lines, the main communication and bus control circuit including integrated circuitry for generating and receiving control signals on the control signal lines and for transferring a first byte of the digital information between the first byte-wide group of data lines and the device; a plurality of modular interface extension circuits each coupled to a common one of the control signal lines and each coupled to a dedicated one of the additional byte-wide groups of data lines, each modular interface extension circuit including circuitry for transferring an additional byte of the digital information between its respective byte-wide group of data lines and the device, the transfers of the first and the additional bytes of the digital information being synchronized by a signal from the external bus on the common control signal line; circuitry for transferring the first byte of the digital information between the main communication and bus control circuit and the device; circuitry for transferring the additional bytes of the digital information between the plurality of modular interface extension circuits and the device; and a sequential logic circuit for controlling, in accordance with instructions from the microprocessor, parallel transfer of the first and the additional bytes of the digital information between the external bus and the device when the sequential logic circuit receives a signal from the microprocessor indicating that the digital information is message, status, or command information.
Claim 12
Independent Claim
331 words
A system for transferring digital information including message, status, or command information between an external bus and a device that includes a microprocessor for controlling the transfers of the digital information, the external bus including a first byte-wide group of data lines and a plurality of additional byte-wide groups of data lines which carry the digital information, the external bus further including control signal lines which carry control signals that define operating phases of the external bus, the system comprising: a main communication and bus control circuit coupled to the control signal lines and to the first byte-wide group of the data lines, the main communication and bus control circuit including integrated circuitry for generating and receiving control signals on the control signal lines and for transferring a first byte of the digital information between the first byte-wide group of data lines and the device; a plurality of modular interface extension circuits each coupled to a common one of the control signal lines and each coupled to a dedicated one of the additional byte-wide groups of data lines, each modular interface extension circuit including circuitry for transferring an additional byte of the digital information between its respective byte-wide group of data lines and the device, the transfers of the first and the additional bytes of the digital information being synchronized by a signal from the external bus on the common control signal line; circuitry for transferring the first byte of the digital information between the main communication and bus control circuit and the device; circuitry for transferring the additional bytes of the digital information between the plurality of modular interface extension circuits and the device; and a sequential logic circuit for controlling, in accordance with instructions from the microprocessor, parallel transfer of the first and the additional bytes of the digital information between the external bus and the device when the sequential logic circuit receives a signal from the microprocessor indicating that the digital information is message, status, or command information.
Claim 13
Dependent Claim
51 words
The system of claim 9, wherein the main communication and bus control circuit comprises a bi-directional bus interface integrated circuit that generates and receives the control signals including the signal on the common control signal line which synchronizes the transfers of the first and the additional bytes of the digital information.
Claim 14
Dependent Claim
31 words
The system of claim 10, wherein the bi-directional bus interface integrated circuit comprises a first-in, first-out storage circuit which provides the circuitry for transferring the first byte of the digital information.
Claim 15
Dependent Claim
22 words
The system of claim 9, wherein each of the plurality of modular interface extension circuits comprises a bi-directional, first-in, first-out storage circuit.
Claim 16
Dependent Claim
370 words
A mass data storage system for interfacing with a microprocessor, comprising: a mass storage device set; array controller means, coupled to the mass storage device set, for controlling transfers of mass storage data to and from the mass storage device set; device controller means for initiating transfers of digital information including message, status, or command information between the device controller means and the array controller means; a multi-conductor mass storage data communication bus for transferring the digital information between the array controller means and the device controller means, the communication bus having a first byte-wide group of data lines and a plurality of additional byte-wide group of data lines which carry the digital information, and control signal lines which carry control signals that define operating phases of the communication bus; and interface means, associated with the array controller means and associated with the device controller means, for connecting the array controller means and the device controller means to the communication bus, the interface means comprising: a main communication and bus control circuit coupled to the control signal lines and to the first byte-wide group of the data lines, the main communication and bus control circuit including integrated circuitry for generating and receiving the control signals on the control signal lines and for transferring a first byte of the digital information between the first byte-wide group of data lines and the interface means; a plurality of modular interface extension circuits each coupled to a common one of the control signal lines and each coupled to a dedicated one of the additional byte-wide groups of data lines, each modular interface extension circuit including circuitry for transferring an additional byte of the digital information between its respective byte-wide group of data lines and the interface means, the transfers of the first and the additional bytes of the digital information being synchronized by a signal from the external bus on the common control signal line; and sequential logic means for controlling parallel transfer of the first and the additional bytes of the digital information between the external bus and the interface means when the sequential logic means receives a signal from the microprocessor indicating that the digital information is message, status, or command information.
Claim 17
Dependent Claim
370 words
A mass data storage system for interfacing with a microprocessor, comprising: a mass storage device set; array controller means, coupled to the mass storage device set, for controlling transfers of mass storage data to and from the mass storage device set; device controller means for initiating transfers of digital information including message, status, or command information between the device controller means and the array controller means; a multi-conductor mass storage data communication bus for transferring the digital information between the array controller means and the device controller means, the communication bus having a first byte-wide group of data lines and a plurality of additional byte-wide group of data lines which carry the digital information, and control signal lines which carry control signals that define operating phases of the communication bus; and interface means, associated with the array controller means and associated with the device controller means, for connecting the array controller means and the device controller means to the communication bus, the interface means comprising: a main communication and bus control circuit coupled to the control signal lines and to the first byte-wide group of the data lines, the main communication and bus control circuit including integrated circuitry for generating and receiving the control signals on the control signal lines and for transferring a first byte of the digital information between the first byte-wide group of data lines and the interface means; a plurality of modular interface extension circuits each coupled to a common one of the control signal lines and each coupled to a dedicated one of the additional byte-wide groups of data lines, each modular interface extension circuit including circuitry for transferring an additional byte of the digital information between its respective byte-wide group of data lines and the interface means, the transfers of the first and the additional bytes of the digital information being synchronized by a signal from the external bus on the common control signal line; and sequential logic means for controlling parallel transfer of the first and the additional bytes of the digital information between the external bus and the interface means when the sequential logic means receives a signal from the microprocessor indicating that the digital information is message, status, or command information.
Claim 18
Dependent Claim
54 words
The mass data storage system of claim 13, wherein the main communication and bus control circuit comprises a bi-directional bus interface integrated circuit that generates and receives the control signals including the signal on the common control signal line which synchronizes the transfers of the first and the additional bytes of the digital information.
Claim 19
Dependent Claim
34 words
The mass data storage system of claim 14, wherein the bi-directional bus interface integrated circuit comprises a first-in, first-out storage circuit which provides the circuitry for transferring the first byte of the digital information.
Claim 20
Dependent Claim
25 words
The mass data storage system of claim 13, wherein each of the plurality of modular interface extension circuits comprises a bi-directional, first-in, first-out storage circuit.
Claim 21
Independent Claim
331 words
A system for transferring digital information including message, status, or command information between an external bus and a device that includes a microprocessor for controlling the transfers of the digital information, the external bus including a first byte-wide group of data lines and a plurality of additional byte-wide groups of data lines which carry the digital information, the external bus further including control signal lines which carry control signals that define operating states of the external bus, the system comprising: a main communication and bus control circuit coupled to the control signal lines and to the first byte-wide group of the data lines, the main communication and bus control circuit including integrated circuitry for generating and receiving control signals on the control signal lines and for transferring a first byte of the digital information between the first byte-wide group of data lines and the device; a plurality of modular interface extension circuits each coupled to a common one of the control signal lines and each coupled to a dedicated one of the additional byte-wide groups of data lines, each modular interface extension circuit including circuitry for transferring an additional byte of the digital information between its respective byte-wide group of data lines and the device, the transfers of the first and the additional bytes of the digital information being synchronized by a signal from the external bus on the common control signal line; circuitry for transferring the first byte of the digital information between the main communication and bus control circuit and the device; circuitry for transferring the additional bytes of the digital information between the plurality of modular interface extension circuits and the device; and a sequential logic circuit for controlling, in accordance with instructions from the microprocessor, parallel transfer of the first and the additional bytes of the digital information between the external bus and the device when the sequential logic circuit receives a signal from the microprocessor indicating that the digital information is message, status, or command information.
Claim 22
Independent Claim
331 words
A system for transferring digital information including message, status, or command information between an external bus and a device that includes a microprocessor for controlling the transfers of the digital information, the external bus including a first byte-wide group of data lines and a plurality of additional byte-wide groups of data lines which carry the digital information, the external bus further including control signal lines which carry control signals that define operating states of the external bus, the system comprising: a main communication and bus control circuit coupled to the control signal lines and to the first byte-wide group of the data lines, the main communication and bus control circuit including integrated circuitry for generating and receiving control signals on the control signal lines and for transferring a first byte of the digital information between the first byte-wide group of data lines and the device; a plurality of modular interface extension circuits each coupled to a common one of the control signal lines and each coupled to a dedicated one of the additional byte-wide groups of data lines, each modular interface extension circuit including circuitry for transferring an additional byte of the digital information between its respective byte-wide group of data lines and the device, the transfers of the first and the additional bytes of the digital information being synchronized by a signal from the external bus on the common control signal line; circuitry for transferring the first byte of the digital information between the main communication and bus control circuit and the device; circuitry for transferring the additional bytes of the digital information between the plurality of modular interface extension circuits and the device; and a sequential logic circuit for controlling, in accordance with instructions from the microprocessor, parallel transfer of the first and the additional bytes of the digital information between the external bus and the device when the sequential logic circuit receives a signal from the microprocessor indicating that the digital information is message, status, or command information.
Claim 23
Dependent Claim
51 words
The system of claim 17, wherein the main communication and bus control circuit comprises a bi-directional bus interface integrated circuit that generates and receives the control signals including the signal on the common control signal line which synchronizes the transfers of the first and the additional bytes of the digital information.
Claim 24
Dependent Claim
31 words
The system of claim 18, wherein the bi-directional bus interface integrated circuit comprises a first-in, first-out storage circuit which provides the circuitry for transferring the first byte of the digital information.
Claim 25
Dependent Claim
22 words
The system of claim 17, wherein each of the plurality of modular interface extension circuits comprises a bi-directional, first-in, first-out storage circuit.
Claim 26
Dependent Claim
370 words
A mass data storage system for interfacing with a microprocessor, comprising: a mass storage device set; array controller means, coupled to the mass storage device set, for controlling transfers of mass storage data to and from the mass storage device set; device controller means for initiating transfers of digital information including message, status, or command information between the device controller means and the array controller means; a multi-conductor mass storage data communication bus for transferring the digital information between the array controller means and the device controller means, the communication bus having a first byte-wide group of data lines and a plurality of additional byte-wide group of data lines which carry the digital information, and control signal lines which carry control signals that define operating states of the communication bus; and interface means, associated with the array controller means and associated with the device controller means, for connecting the array controller means and the device controller means to the communication bus, the interface means comprising: a main communication and bus control circuit coupled to the control signal lines and to the first byte-wide group of the data lines, the main communication and bus control circuit including integrated circuitry for generating and receiving the control signals on the control signal lines and for transferring a first byte of the digital information between the first byte-wide group of data lines and the interface means; a plurality of modular interface extension circuits each coupled to a common one of the control signal lines and each coupled to a dedicated one of the additional byte-wide groups of data lines, each modular interface extension circuit including circuitry for transferring an additional byte of the digital information between its respective byte-wide group of data lines and the interface means, the transfers of the first and the additional bytes of the digital information being synchronized by a signal from the external bus on the common control signal line; and sequential logic means for controlling parallel transfer of the first and the additional bytes of the digital information between the external bus and the interface means when the sequential logic means receives a signal from the microprocessor indicating that the digital information is message, status, or command information.
Claim 27
Dependent Claim
370 words
A mass data storage system for interfacing with a microprocessor, comprising: a mass storage device set; array controller means, coupled to the mass storage device set, for controlling transfers of mass storage data to and from the mass storage device set; device controller means for initiating transfers of digital information including message, status, or command information between the device controller means and the array controller means; a multi-conductor mass storage data communication bus for transferring the digital information between the array controller means and the device controller means, the communication bus having a first byte-wide group of data lines and a plurality of additional byte-wide group of data lines which carry the digital information, and control signal lines which carry control signals that define operating states of the communication bus; and interface means, associated with the array controller means and associated with the device controller means, for connecting the array controller means and the device controller means to the communication bus, the interface means comprising: a main communication and bus control circuit coupled to the control signal lines and to the first byte-wide group of the data lines, the main communication and bus control circuit including integrated circuitry for generating and receiving the control signals on the control signal lines and for transferring a first byte of the digital information between the first byte-wide group of data lines and the interface means; a plurality of modular interface extension circuits each coupled to a common one of the control signal lines and each coupled to a dedicated one of the additional byte-wide groups of data lines, each modular interface extension circuit including circuitry for transferring an additional byte of the digital information between its respective byte-wide group of data lines and the interface means, the transfers of the first and the additional bytes of the digital information being synchronized by a signal from the external bus on the common control signal line; and sequential logic means for controlling parallel transfer of the first and the additional bytes of the digital information between the external bus and the interface means when the sequential logic means receives a signal from the microprocessor indicating that the digital information is message, status, or command information.
Claim 28
Dependent Claim
54 words
The mass data storage system of claim 21, wherein the main communication and bus control circuit comprises a bi-directional bus interface integrated circuit that generates and receives the control signals including the signal on the common control signal line which synchronizes the transfers of the first and the additional bytes of the digital information.
Claim 29
Dependent Claim
34 words
The mass data storage system of claim 22, wherein the bi-directional bus interface integrated circuit comprises a first-in, first-out storage circuit which provides the circuitry for transferring the first byte of the digital information.
Claim 30
Dependent Claim
25 words
The mass data storage system of claim 21, wherein each of the plurality of modular interface extension circuits comprises a bi-directional, first-in, first-out storage circuit.
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USPTO Annuity & Maintenance Windows
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| 3.5 Years (Year 4) | 1998-09-25 | 1999-03-27 | 1999-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-25 | 2003-03-27 | 2003-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-25 | 2007-03-27 | 2007-09-26 | $7700.00 | Window Closed / Lapsed |