US5454093A — Buffer bypass for quick data access

Claim 1

Independent Claim 199 words

A computer system comprising: a data processor; a main memory; a cache memory coupled to said main memory to receive data therefrom and coupled to said processor to transfer data thereto; a data buffer coupled to said main memory to receive data therefrom and coupled to said cache memory to transfer data thereto; means for transferring one part of a block of data from said main memory to said cache memory for access by said processor without prior transfer of said one part of said block of data to said data buffer, and then transferring all of said block of data except said one part to said data buffer while said processor has access to said one part of said block of data in said cache memory; and means for subsequently transferring said all of said block of data except said one part from said data buffer to said cache memory and combining said all of said block of data except said one part with said one part which is already stored in said cache memory, whereby said one part in said cache memory is not transferred from said data buffer to complete said block in said cache memory.

Claim 2

Dependent Claim 199 words

A computer system comprising: a data processor; a main memory; a cache memory coupled to said main memory to receive data therefrom and coupled to said processor to transfer data thereto; a data buffer coupled to said main memory to receive data therefrom and coupled to said cache memory to transfer data thereto; means for transferring one part of a block of data from said main memory to said cache memory for access by said processor without prior transfer of said one part of said block of data to said data buffer, and then transferring all of said block of data except said one part to said data buffer while said processor has access to said one part of said block of data in said cache memory; and means for subsequently transferring said all of said block of data except said one part from said data buffer to said cache memory and combining said all of said block of data except said one part with said one part which is already stored in said cache memory, whereby said one part in said cache memory is not transferred from said data buffer to complete said block in said cache memory.

Claim 3

Dependent Claim 22 words

A computer system as set forth in claim 1 wherein said processor is coupled to said data buffer to read data therefrom.

Claim 4

Dependent Claim 44 words

A computer system as set forth in claim 1 wherein said one part of said block of data is transferred to said cache memory in response to a request by said processor for data included in said one part of said block of data.

Claim 5

Dependent Claim 49 words

A computer system as set forth in claim 3 wherein another part of said block of data which was transferred to said data buffer is likely to be needed by said processor soon after said processor processes said one part of said block of data in said cache memory.

Claim 6

Dependent Claim 171 words

A computer system comprising: a data processor; a main memory; a cache memory coupled to said main memory to receive data therefrom and coupled to said processor to transfer data thereto; a data buffer coupled to said main memory to receive data therefrom and coupled to said cache memory to transfer data thereto; means for transferring one part of a block of data from said main memory to said cache memory for access by said processor without prior transfer of said one part of said block of data to said data buffer, and transferring another part of said block of data to said data buffer; first clock means, coupled to said processor, for timing access by said processor to said one part of said block of data in said cache memory; and second clock means, coupled to said main memory, for timing transfer of data from said main memory to said cache memory and said data buffer, said first clock means having a different cycle time than said second clock means.

Claim 7

Dependent Claim 171 words

A computer system comprising: a data processor; a main memory; a cache memory coupled to said main memory to receive data therefrom and coupled to said processor to transfer data thereto; a data buffer coupled to said main memory to receive data therefrom and coupled to said cache memory to transfer data thereto; means for transferring one part of a block of data from said main memory to said cache memory for access by said processor without prior transfer of said one part of said block of data to said data buffer, and transferring another part of said block of data to said data buffer; first clock means, coupled to said processor, for timing access by said processor to said one part of said block of data in said cache memory; and second clock means, coupled to said main memory, for timing transfer of data from said main memory to said cache memory and said data buffer, said first clock means having a different cycle time than said second clock means.

Claim 8

Independent Claim 113 words

A method for providing access by a computer processor to data stored in memory, said method comprising the steps of: transferring data requested by said processor to a cache, bypassing an inpage buffer; after transferring the requested data to said cache, transferring other data to said inpage buffer; and providing access by said processor to said requested data in said cache while said other data is transferred to said inpage buffer; and wherein said processor reads said requested data in said cache at a first rate determined by a first clock cycle, and said other data is transferred to said inpage buffer at a second rate determined by a second, different clock cycle.

Claim 9

Independent Claim 113 words

A method for providing access by a computer processor to data stored in memory, said method comprising the steps of: transferring data requested by said processor to a cache, bypassing an inpage buffer; after transferring the requested data to said cache, transferring other data to said inpage buffer; and providing access by said processor to said requested data in said cache while said other data is transferred to said inpage buffer; and wherein said processor reads said requested data in said cache at a first rate determined by a first clock cycle, and said other data is transferred to said inpage buffer at a second rate determined by a second, different clock cycle.

Claim 10

Dependent Claim 31 words

A method as set forth in claim 6 further comprising the step of fetching different data from said memory while transferring said other data from said inpage buffer to said cache.

Claim 11

Dependent Claim 156 words

A computer system comprising: a data processor; first clock means, coupled to said processor, for timing operation of said data processor; a main memory; a cache memory coupled to said main memory to receive data therefrom and coupled to said processor to transfer data thereto; a data buffer coupled to said main memory to receive data therefrom, coupled to said cache memory to transfer data thereto, and coupled to said processor to transfer data thereto; second clock means, coupled to said main memory, for timing transfer of data from said main memory to said cache memory and said data buffer, said first clock means having a different cycle time than said second clock means; and means for timing operation of said data buffer with said first clock means and said second clock means during different operations and timing operation of said cache memory with said first clock means and said second clock means during different operations.

Claim 12

Dependent Claim 156 words

A computer system comprising: a data processor; first clock means, coupled to said processor, for timing operation of said data processor; a main memory; a cache memory coupled to said main memory to receive data therefrom and coupled to said processor to transfer data thereto; a data buffer coupled to said main memory to receive data therefrom, coupled to said cache memory to transfer data thereto, and coupled to said processor to transfer data thereto; second clock means, coupled to said main memory, for timing transfer of data from said main memory to said cache memory and said data buffer, said first clock means having a different cycle time than said second clock means; and means for timing operation of said data buffer with said first clock means and said second clock means during different operations and timing operation of said cache memory with said first clock means and said second clock means during different operations.

Claim 13

Dependent Claim 85 words

A computer system as set forth in claim 8 wherein the timing means comprises means for applying said second clock means to time said data buffer to permit said main memory to transfer data to said data buffer, means for applying said first clock means to time said data buffer to permit said processor to read data from said data buffer, and means for applying said first clock means to time said cache memory to permit said processor to read data from said cache memory.

Claim 14

Dependent Claim 82 words

A computer system as set forth in claim 8 wherein the timing means comprises: means for applying said second clock means to time said data buffer to permit transfer of main memory data to said data buffer, and applying said first clock means to time said cache memory while said second clock means is applied to time said data buffer, to permit said processor to read data from said cache memory while said main memory data is transferred to said data buffer.

Claim 15

Dependent Claim 38 words

A computer system as set forth in claim 8 further comprising means for transferring part of a block of main memory data to said cache memory without prior transfer of the block data part to said data buffer.

Claim 16

Dependent Claim 26 words

A computer system as set forth in claim 11 further comprising means for transferring a remaining part of said block of data to said data buffer.

Claim 17

Dependent Claim 64 words

A computer system as set forth in claim 8 further comprising means for transferring data requested by said processor to said cache memory bypassing said data buffer while said second clock means is applied to time said cache memory, and then applying said first clock means to time said cache memory to permit said processor to read said requested data from said cache memory.

Claim 18

Dependent Claim 50 words

A computer system as set forth in claim 13 further comprising means for transferring additional data associated with the requested data to said data buffer with timing by said second clock means while said processor reads said requested data from said cache memory with timing by said first clock means.

Claim 19

Dependent Claim 45 words

A computer system as set forth in claim 14 wherein said requested data and said additional data are part of one data page and were stored logically adjacent to each other in main memory before being transferred to said cache memory and said data buffer.

Claim 20

Dependent Claim 41 words

A computer system as set forth in claim 14 further comprising means for applying said first clock means to time said data buffer after transferring said additional data to said data buffer to permit said processor to access said additional data.

Claim 21

Dependent Claim 25 words

A computer system as set forth in claim 14 further comprising means for transferring said additional data from said data buffer to said cache memory.

Claim 22

Dependent Claim 45 words

A computer system as set forth in claim 17 wherein said timing means applies said first clock means simultaneously to time both said data buffer and said cache memory to permit said additional data to be transferred from said data buffer to said cache memory.

Claim 23

Dependent Claim 42 words

A computer system as set forth in claim 8 wherein said first clock means is applied simultaneously to time both said data buffer and said cache memory to permit said processor to read data from said data buffer and said cache memory.

Claim 24

Dependent Claim 65 words

A computer system as set forth in claim 8 wherein the timing means comprises: means for controlling access to said cache memory and said data buffer; and means, coupled to said controlling means, for selecting either said first clock means or said second clock means to time said data buffer and said cache memory based at least in part on outputs of said controlling means.

Claim 25

Dependent Claim 26 words

A computer system as set forth in claim 8 wherein said first clock means and said second clock means are segments of a common base clock.

Claim 26

Dependent Claim 67 words

A computer system as set forth in claim 8 further comprising: means for transferring part of a block of data to said cache memory and transferring another part of said block of data to said data buffer, and subsequently transferring said other part of said block of data from said data buffer to said cache memory while another block of data is fetched from said main memory.

Claim 27

Dependent Claim 38 words

A computer system as set forth in claim 22 wherein the timing means times the transfer of said other part of said block of data from said data buffer to said cache memory with said first clock means.

Claim 28

Dependent Claim 75 words

A computer system as set forth in claim 8 further comprising: means for controlling data output from said main memory; and means for timing operation of the controlling means with said first clock means to enable said controlling means to respond to communications originating from said processor, and timing operation of said controlling means with said second clock means to enable data transfer from said main memory to said cache memory and said data buffer.

Claim 29

Dependent Claim 27 words

A computer system as set forth in claim 8 wherein said data buffer is an inpage buffer and has a substantially lower capacity than said cache memory.

Claim 30

Dependent Claim 27 words

A computer system as set forth in claim 8 wherein said first clock means comprises a plurality of non-overlapping, periodic timing signals having the same cycle time.

Claim 31

Dependent Claim 27 words

A computer system as set forth in claim 8 wherein said second clock means comprises a plurality of non-overlapping, periodic timing signals having the same cycle time.

Claim 32

Dependent Claim 184 words

A computer system comprising: a data processor; first timing means, coupled to said processor, for timing operation of said data processor; a main memory; a cache memory coupled to said main memory to receive data therefrom and coupled to said processor to transfer data thereto; a data buffer coupled to said main memory to receive data therefrom, coupled to said cache memory to transfer data thereto, and coupled to said processor to transfer data thereto; second timing means, coupled to said main memory, for timing transfer of main memory data to said cache memory and said data buffer, said first timing means having a different cycle time than said second timing means; and means for applying said second timing means to time said data buffer to permit transfer of data originating from said main memory to said data buffer, and applying said first timing means to time said cache memory while said second timing means times said data buffer, to permit said processor to read data from said cache memory while said data originating from said main memory is transferred to said data buffer.

Claim 33

Dependent Claim 184 words

A computer system comprising: a data processor; first timing means, coupled to said processor, for timing operation of said data processor; a main memory; a cache memory coupled to said main memory to receive data therefrom and coupled to said processor to transfer data thereto; a data buffer coupled to said main memory to receive data therefrom, coupled to said cache memory to transfer data thereto, and coupled to said processor to transfer data thereto; second timing means, coupled to said main memory, for timing transfer of main memory data to said cache memory and said data buffer, said first timing means having a different cycle time than said second timing means; and means for applying said second timing means to time said data buffer to permit transfer of data originating from said main memory to said data buffer, and applying said first timing means to time said cache memory while said second timing means times said data buffer, to permit said processor to read data from said cache memory while said data originating from said main memory is transferred to said data buffer.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1998-09-25	1999-03-27	1999-09-26	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2002-09-25	2003-03-27	2003-09-26	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2006-09-25	2007-03-27	2007-09-26	$7700.00	Window Closed / Lapsed

Buffer bypass for quick data access

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