System and method for peripheral data transfer

Claim 1

A system for transferring data between a host computer and a printer, comprising: an output interface on the host computer to transfer a byte of printer data to the printer by apportioning said byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, each of said second portions also containing a parity data bit; an input register within the printer to receive said first and second transmitted data bytes and temporarily store said first and second transmitted data bytes; a parity error checker, coupled to said input register, to analyze said stored first and second transmitted data bytes and generate a parity error signal if a parity error occurred within said first and second transmitted data bytes; a clock detection circuit, coupled to said input registers, to receive said first and second clock signals from said stored first and second transmitted data bytes, said clock detection circuit generating a first delayed signal when said first clock signal has made a transition from said first logic level to said second logic level and said second clock signal has made a transition from said second logic level to said first logic level, and generating a second delayed signal when said first clock signal has made a transition from said second logic level to said first logic level and said second clock signal has made a transition from said first logic level to said second logic level; a first storage register, coupled to said input register and enabled by said first delayed signal, to store said first portion of said stored first transmitted data byte when said first delayed signal is received; and a second storage register, coupled to said input register and enabled by said second delayed signal, to store said first portion of said stored second transmitted data byte when said second delayed signal is received, whereby said first portions of said stored first and second transmitted data bytes are transmitted from the host computer to the printer and can be reformed as said byte of printer data.

Claim 2

A system for transferring data between a host computer and a printer, comprising: an output interface on the host computer to transfer a byte of printer data to the printer by apportioning said byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, each of said second portions also containing a parity data bit; an input register within the printer to receive said first and second transmitted data bytes and temporarily store said first and second transmitted data bytes; a parity error checker, coupled to said input register, to analyze said stored first and second transmitted data bytes and generate a parity error signal if a parity error occurred within said first and second transmitted data bytes; a clock detection circuit, coupled to said input registers, to receive said first and second clock signals from said stored first and second transmitted data bytes, said clock detection circuit generating a first delayed signal when said first clock signal has made a transition from said first logic level to said second logic level and said second clock signal has made a transition from said second logic level to said first logic level, and generating a second delayed signal when said first clock signal has made a transition from said second logic level to said first logic level and said second clock signal has made a transition from said first logic level to said second logic level; a first storage register, coupled to said input register and enabled by said first delayed signal, to store said first portion of said stored first transmitted data byte when said first delayed signal is received; and a second storage register, coupled to said input register and enabled by said second delayed signal, to store said first portion of said stored second transmitted data byte when said second delayed signal is received, whereby said first portions of said stored first and second transmitted data bytes are transmitted from the host computer to the printer and can be reformed as said byte of printer data.

Claim 6

A system for transferring data between a host computer and a printer, comprising: an output interface on the host computer to transfer a byte of printer data to the printer by apportioning said byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, each of said second portions also containing a parity data bit: a clock detection circuit to receive said first and second clock signals from said first and second transmitted data bytes, said clock detection circuit generating a first delayed signal when said first clock signal has made a transition from said first logic level to said second logic level and said second clock signal has made a transition from said second logic level to said first logic level, and generating a second delayed signal when said first clock signal has made a transition from said second logic level to said first logic level and said second clock signal has made a transition from said first logic level to said second logic level; a first storage register enabled by said first delayed signal, to store said first portion of said first transmitted data byte when said first delayed signal is received; and a second storage register enabled by said second delayed signal, to store said first portion of said second transmitted data byte when said second delayed signal is received, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the printer and can be reformed as said byte of printer data.

Claim 7

A system for transferring data between a host computer and a printer, comprising: an output interface on the host computer to transfer a byte of printer data to the printer by apportioning said byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, each of said second portions also containing a parity data bit: a clock detection circuit to receive said first and second clock signals from said first and second transmitted data bytes, said clock detection circuit generating a first delayed signal when said first clock signal has made a transition from said first logic level to said second logic level and said second clock signal has made a transition from said second logic level to said first logic level, and generating a second delayed signal when said first clock signal has made a transition from said second logic level to said first logic level and said second clock signal has made a transition from said first logic level to said second logic level; a first storage register enabled by said first delayed signal, to store said first portion of said first transmitted data byte when said first delayed signal is received; and a second storage register enabled by said second delayed signal, to store said first portion of said second transmitted data byte when said second delayed signal is received, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the printer and can be reformed as said byte of printer data.

Claim 10

A system for transferring data between a host computer and a printer, the host computer containing an output interface on the host computer to transfer a byte of printer data to the printer by apportioning said byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, each of said second portions also containing a parity data bit, the system comprising: an input register within the printer to receive the first and second transmitted data bytes and temporarily store the first and second transmitted data bytes; a parity error checker, coupled to said input register, to analyze said stored first and second transmitted data bytes and generate a parity error signal if a parity error occurred within the first and second transmitted data bytes; a clock detection circuit, coupled to said input registers, to receive said first and second clock signals from said stored first and second transmitted data bytes, said clock detection circuit generating a first delayed signal when said first clock signal has made a transition from said first logic level to said second logic level and said second clock signal has made a transition from said second logic level to said first logic level, and generating a second delayed signal when said first clock signal has made a transition from said second logic level to said first logic level and said second clock signal has made a transition from said first logic level to said second logic level; a first storage register, coupled to said input register and enabled by said first delayed signal, to store said first portion of said stored first transmitted data byte when said first delayed signal is received; and a second storage register, coupled to said input register and enabled by said second delayed signal, to store said first portion of said stored second transmitted data byte when said second delayed signal is received, whereby said first portions of said stored first and second transmitted data bytes are transmitted from the host computer to the printer and can be reformed as said byte of printer data.

Claim 11

A system for transferring data between a host computer and a printer, the host computer containing an output interface on the host computer to transfer a byte of printer data to the printer by apportioning said byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, each of said second portions also containing a parity data bit, the system comprising: an input register within the printer to receive the first and second transmitted data bytes and temporarily store the first and second transmitted data bytes; a parity error checker, coupled to said input register, to analyze said stored first and second transmitted data bytes and generate a parity error signal if a parity error occurred within the first and second transmitted data bytes; a clock detection circuit, coupled to said input registers, to receive said first and second clock signals from said stored first and second transmitted data bytes, said clock detection circuit generating a first delayed signal when said first clock signal has made a transition from said first logic level to said second logic level and said second clock signal has made a transition from said second logic level to said first logic level, and generating a second delayed signal when said first clock signal has made a transition from said second logic level to said first logic level and said second clock signal has made a transition from said first logic level to said second logic level; a first storage register, coupled to said input register and enabled by said first delayed signal, to store said first portion of said stored first transmitted data byte when said first delayed signal is received; and a second storage register, coupled to said input register and enabled by said second delayed signal, to store said first portion of said stored second transmitted data byte when said second delayed signal is received, whereby said first portions of said stored first and second transmitted data bytes are transmitted from the host computer to the printer and can be reformed as said byte of printer data.

Claim 12

A system for transferring data between a host computer and a printer, the host computer containing an output interface on the host computer to transfer a byte of printer data to the printer by apportioning said byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, the system comprising: a clock detection circuit to receive the first and second clock signals from the first and second transmitted data bytes, said clock detection circuit generating a first delayed signal when the first clock signal has made a transition from the first logic level to the second logic level and the second clock signal has made a transition from the second logic level to the first logic level, and generating a second delayed signal when the first clock signal has made a transition from the second logic level to the first logic level and the second clock signal has made a transition from the first logic level to the second logic level; a first storage register enabled by said first delayed signal, to store the first portion of the first transmitted data byte when said first delayed signal is received; and a second storage register enabled by said second delayed signal, to store the first portion of the second transmitted data byte when said second delayed signal is received, whereby the stored first portions of the first and second bytes of data are transmitted from the host computer to the printer and can be reformed as the byte of printer data.

Claim 13

A system for transferring data between a host computer and a printer, the host computer containing an output interface on the host computer to transfer a byte of printer data to the printer by apportioning said byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, the system comprising: a clock detection circuit to receive the first and second clock signals from the first and second transmitted data bytes, said clock detection circuit generating a first delayed signal when the first clock signal has made a transition from the first logic level to the second logic level and the second clock signal has made a transition from the second logic level to the first logic level, and generating a second delayed signal when the first clock signal has made a transition from the second logic level to the first logic level and the second clock signal has made a transition from the first logic level to the second logic level; a first storage register enabled by said first delayed signal, to store the first portion of the first transmitted data byte when said first delayed signal is received; and a second storage register enabled by said second delayed signal, to store the first portion of the second transmitted data byte when said second delayed signal is received, whereby the stored first portions of the first and second bytes of data are transmitted from the host computer to the printer and can be reformed as the byte of printer data.

Claim 16

A system for transferring data between a host computer and a printer, the host computer containing an output interface on the host computer to transfer a byte of printer data to the printer by apportioning said byte of printer data into a first portion of first and second transmitted data bytes, the first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, the second clock signal being a logically inverted version of the first clock signal, the system comprising: a clock detection circuit to receive the first and second clock signals from the first and second transmitted data bytes and generate first and second delayed signals; a first storage register enabled by said first delayed signal, to store the first portion of the first transmitted data byte when said first delayed signal is received; and a second storage register enabled by said second delayed signal, to store the first portion of the second transmitted data byte when said second delayed signal is received, whereby the stored first portions of the first and second bytes of data are transmitted from the host computer to the printer and can be reformed as the byte of printer data.

Claim 17

A system for transferring data between a host computer and a printer, the host computer containing an output interface on the host computer to transfer a byte of printer data to the printer by apportioning said byte of printer data into a first portion of first and second transmitted data bytes, the first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, the second clock signal being a logically inverted version of the first clock signal, the system comprising: a clock detection circuit to receive the first and second clock signals from the first and second transmitted data bytes and generate first and second delayed signals; a first storage register enabled by said first delayed signal, to store the first portion of the first transmitted data byte when said first delayed signal is received; and a second storage register enabled by said second delayed signal, to store the first portion of the second transmitted data byte when said second delayed signal is received, whereby the stored first portions of the first and second bytes of data are transmitted from the host computer to the printer and can be reformed as the byte of printer data.

Claim 20

A system for transferring data between a host computer and a printer, the printer containing a clock detection circuit to receive first and second clock signals from the host computer and generate first and second delayed signals and first and second storage registers enabled by the first and second delayed signals, respectively, to store portions of the data transmitted from the host computer, the system comprising: a data file within the host computer storing a plurality of bytes of printer data to be transmitted from the host computer to the printer; and an output interface on the host computer to transfer each of said plurality of bytes of printer data to the printer by apportioning each of said byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing the first and second clock signals each having first and second logic levels, the second clock signal being a logically inverted version of the first clock signal.

Claim 21

A system for transferring data between a host computer and a printer, the printer containing a clock detection circuit to receive first and second clock signals from the host computer and generate first and second delayed signals and first and second storage registers enabled by the first and second delayed signals, respectively, to store portions of the data transmitted from the host computer, the system comprising: a data file within the host computer storing a plurality of bytes of printer data to be transmitted from the host computer to the printer; and an output interface on the host computer to transfer each of said plurality of bytes of printer data to the printer by apportioning each of said byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing the first and second clock signals each having first and second logic levels, the second clock signal being a logically inverted version of the first clock signal.

Claim 23

A system for transferring data between a host computer and a peripheral, comprising: an output interface on the host computer to transfer a byte of peripheral data to the peripheral by apportioning said byte of peripheral data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, each of said second portions also containing a parity data bit; a clock detection circuit to receive said first and second clock signals from said first and second transmitted data bytes, said clock detection circuit generating a first delayed signal when said first clock signal has made a transition from said first logic level to said second logic level and said second clock signal has made a transition from said second logic level to said first logic level, and generating a second delayed signal when said first clock signal has made a transition from said second logic level to said first logic level and said second clock signal has made a transition from said first logic level to said second logic level; a first storage register enabled by said first delayed signal, to store said first portion of said first transmitted data byte when said first delayed signal is received; and a second storage register enabled by said second delayed signal, to store said first portion of said second transmitted data byte when said second delayed signal is received, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the peripheral and can be reformed as said byte of peripheral data.

Claim 24

A system for transferring data between a host computer and a peripheral, comprising: an output interface on the host computer to transfer a byte of peripheral data to the peripheral by apportioning said byte of peripheral data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, each of said second portions also containing a parity data bit; a clock detection circuit to receive said first and second clock signals from said first and second transmitted data bytes, said clock detection circuit generating a first delayed signal when said first clock signal has made a transition from said first logic level to said second logic level and said second clock signal has made a transition from said second logic level to said first logic level, and generating a second delayed signal when said first clock signal has made a transition from said second logic level to said first logic level and said second clock signal has made a transition from said first logic level to said second logic level; a first storage register enabled by said first delayed signal, to store said first portion of said first transmitted data byte when said first delayed signal is received; and a second storage register enabled by said second delayed signal, to store said first portion of said second transmitted data byte when said second delayed signal is received, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the peripheral and can be reformed as said byte of peripheral data.

Claim 27

A system for transferring data between a host computer and a peripheral, the host computer containing an output interface on the host computer to transfer a byte of peripheral data to the peripheral by apportioning said byte of peripheral data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, the system comprising: a clock detection circuit to receive the first and second clock signals from the first and second transmitted data bytes, said clock detection circuit generating a first delayed signal when the first clock signal has made a transition from the first logic level to the second logic level and the second clock signal has made a transition from the second logic level to the first logic level, and generating a second delayed signal when the first clock signal has made a transition from the second logic level to the first logic level and the second clock signal has made a transition from the first logic level to the second logic level; a first storage register enabled by said first delayed signal, to store the first portion of the first transmitted data byte when said first delayed signal is received; and a second storage register enabled by said second delayed signal, to store the first portion of the second transmitted data byte when said second delayed signal is received, whereby the stored first portions of the first and second bytes of data are transmitted from the host computer to the peripheral and can be reformed as the byte of peripheral data.

Claim 28

A system for transferring data between a host computer and a peripheral, the host computer containing an output interface on the host computer to transfer a byte of peripheral data to the peripheral by apportioning said byte of peripheral data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, the system comprising: a clock detection circuit to receive the first and second clock signals from the first and second transmitted data bytes, said clock detection circuit generating a first delayed signal when the first clock signal has made a transition from the first logic level to the second logic level and the second clock signal has made a transition from the second logic level to the first logic level, and generating a second delayed signal when the first clock signal has made a transition from the second logic level to the first logic level and the second clock signal has made a transition from the first logic level to the second logic level; a first storage register enabled by said first delayed signal, to store the first portion of the first transmitted data byte when said first delayed signal is received; and a second storage register enabled by said second delayed signal, to store the first portion of the second transmitted data byte when said second delayed signal is received, whereby the stored first portions of the first and second bytes of data are transmitted from the host computer to the peripheral and can be reformed as the byte of peripheral data.

Claim 31

A system for transferring data between a host computer and a peripheral, the host computer containing an output interface on the host computer to transfer a byte of peripheral data to the peripheral by apportioning said byte of peripheral data into a first portion of first and second transmitted data bytes, the first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, the second clock signal being a logically inverted version of the first clock signal, the system comprising: a clock detection circuit to receive the first and second clock signals from the first and second transmitted data bytes and generate first and second delayed signals; a first storage register enabled by said first delayed signal, to store the first portion of the first transmitted data byte when said first delayed signal is received; and a second storage register enabled by said second delayed signal, to store the first portion of the second transmitted data byte when said second delayed signal is received, whereby the stored first portions of the first and second bytes of data are transmitted from the host computer to the peripheral and can be reformed as the byte of peripheral data.

Claim 32

A system for transferring data between a host computer and a peripheral, the host computer containing an output interface on the host computer to transfer a byte of peripheral data to the peripheral by apportioning said byte of peripheral data into a first portion of first and second transmitted data bytes, the first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, the second clock signal being a logically inverted version of the first clock signal, the system comprising: a clock detection circuit to receive the first and second clock signals from the first and second transmitted data bytes and generate first and second delayed signals; a first storage register enabled by said first delayed signal, to store the first portion of the first transmitted data byte when said first delayed signal is received; and a second storage register enabled by said second delayed signal, to store the first portion of the second transmitted data byte when said second delayed signal is received, whereby the stored first portions of the first and second bytes of data are transmitted from the host computer to the peripheral and can be reformed as the byte of peripheral data.

Claim 35

A method in a host computer system attached to a printer of transferring a byte of data between the host computer and the printer, the method comprising the steps of: (a) apportioning a byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal; (b) transferring said first transmitted data byte with said second portion thereof having said first clock signal at said first logic level; (c) latching said first portion of said first transmitted data byte in a first storage location within the printer following the arrival of both said first and second clock signals within the printer; (d) transferring said second transmitted data byte with said second portion thereof having said first clock signal at said second logic level; and (e) latching said first portion of said second transmitted data byte in a second storage location within the printer following the arrival of both said first and second clock signals within the printer, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the printer and can be reformed as said byte of printer data.

Claim 36

A method in a host computer system attached to a printer of transferring a byte of data between the host computer and the printer, the method comprising the steps of: (a) apportioning a byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal; (b) transferring said first transmitted data byte with said second portion thereof having said first clock signal at said first logic level; (c) latching said first portion of said first transmitted data byte in a first storage location within the printer following the arrival of both said first and second clock signals within the printer; (d) transferring said second transmitted data byte with said second portion thereof having said first clock signal at said second logic level; and (e) latching said first portion of said second transmitted data byte in a second storage location within the printer following the arrival of both said first and second clock signals within the printer, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the printer and can be reformed as said byte of printer data.

Claim 40

A method in a host computer system attached to a printer of transferring a byte of printer data between the host computer and the printer, the byte of printer data being apportioned into a first portion of first and second transmitted data bytes, the first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, the second clock signal being a logically inverted version of the first clock signal, the method comprising the steps of the method comprising the steps of: (a) transferring the first transmitted data byte with the second portion thereof having the first clock signal at the first logic level; (b) latching the first portion of the first transmitted data byte in a first storage location within the printer following the arrival of both the first and second clock signals within the printer; (c) transferring the second transmitted data byte with the second portion thereof having the first clock signal at the second logic level; and (d) latching the first portion of the second transmitted data byte in a second storage location within the printer following the arrival of both the first and second clock signals within the printer, whereby the first portions of the first and second transmitted data bytes are transmitted from the host computer to the printer and can be reformed as the byte of printer data.

Claim 41

A method in a host computer system attached to a printer of transferring a byte of printer data between the host computer and the printer, the byte of printer data being apportioned into a first portion of first and second transmitted data bytes, the first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, the second clock signal being a logically inverted version of the first clock signal, the method comprising the steps of the method comprising the steps of: (a) transferring the first transmitted data byte with the second portion thereof having the first clock signal at the first logic level; (b) latching the first portion of the first transmitted data byte in a first storage location within the printer following the arrival of both the first and second clock signals within the printer; (c) transferring the second transmitted data byte with the second portion thereof having the first clock signal at the second logic level; and (d) latching the first portion of the second transmitted data byte in a second storage location within the printer following the arrival of both the first and second clock signals within the printer, whereby the first portions of the first and second transmitted data bytes are transmitted from the host computer to the printer and can be reformed as the byte of printer data.

Claim 44

A method in a host computer system attached to a printer of transferring a byte of printer data between the host computer and the printer, the byte of printer data being apportioned into a first portion of first and second transmitted data bytes, the first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, the second clock signal being a logically inverted version of the first clock signal, the method comprising the steps of the method comprising the steps of: (a) latching the first portion of the first transmitted data byte in a first storage location within the printer following the arrival of both the first and second clock signals within the printer, the first clock signal having the first logic level; and (b) latching the first portion of the second transmitted data byte in a second storage location within the printer following the arrival of both the first and second clock signals within the printer, the first clock signal having the second logic level.

Claim 45

A method in a host computer system attached to a printer of transferring a byte of printer data between the host computer and the printer, the byte of printer data being apportioned into a first portion of first and second transmitted data bytes, the first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, the second clock signal being a logically inverted version of the first clock signal, the method comprising the steps of the method comprising the steps of: (a) latching the first portion of the first transmitted data byte in a first storage location within the printer following the arrival of both the first and second clock signals within the printer, the first clock signal having the first logic level; and (b) latching the first portion of the second transmitted data byte in a second storage location within the printer following the arrival of both the first and second clock signals within the printer, the first clock signal having the second logic level.

Claim 48

A method of transferring compressed data between a host computer and a printer attached to a parallel printer port on the host computer by a printer cable, the method comprising the steps of: (a) apportioning a byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, said second portion of said first or second transmitted data bytes also containing a signal indicating that said first portion of said first transmitted data byte is a first portion of a count number indicating the number of times that a character is to be repeated by the printer and said first portion of said second transmitted data byte being a second portion of said count number indicating the number of times that a character is to be repeated by the printer; (b) transferring said first transmitted data byte with said second portion thereof having said first clock signal at said first logic level; (c) latching said first portion of said first transmitted data byte in a first storage location within the printer following the arrival of both said first and second clock signals within the printer; (d) transferring said second transmitted data byte with said second portion thereof having said first clock signal at said second logic level; (e) latching said first portion of said second transmitted data byte in a second storage location within the printer following the arrival of both said first and second clock signals within the printer, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the printer and are reformed as said count number; (f) apportioning a byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal; (g) transferring said first transmitted data byte with said second portion thereof having said first clock signal at said first logic level; (h) latching said first portion of said first transmitted data byte in a first storage location within the printer following the arrival of both said first and second clock signals within the printer; (i) transferring said second transmitted data byte with said second portion thereof having said first clock signal at said second logic level; (j) latching said first portion of said second transmitted data byte in a second storage location within the printer following the arrival of both said first and second clock signals within the printer, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the printer and can be reformed as said byte of printer data; and (k) repeatedly printing the character transferred and latched in steps (g)-(h) the number of times represented by said count number resulting from steps (b)-(e).

Claim 49

A method of transferring compressed data between a host computer and a printer attached to a parallel printer port on the host computer by a printer cable, the method comprising the steps of: (a) apportioning a byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal, said second portion of said first or second transmitted data bytes also containing a signal indicating that said first portion of said first transmitted data byte is a first portion of a count number indicating the number of times that a character is to be repeated by the printer and said first portion of said second transmitted data byte being a second portion of said count number indicating the number of times that a character is to be repeated by the printer; (b) transferring said first transmitted data byte with said second portion thereof having said first clock signal at said first logic level; (c) latching said first portion of said first transmitted data byte in a first storage location within the printer following the arrival of both said first and second clock signals within the printer; (d) transferring said second transmitted data byte with said second portion thereof having said first clock signal at said second logic level; (e) latching said first portion of said second transmitted data byte in a second storage location within the printer following the arrival of both said first and second clock signals within the printer, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the printer and are reformed as said count number; (f) apportioning a byte of printer data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal; (g) transferring said first transmitted data byte with said second portion thereof having said first clock signal at said first logic level; (h) latching said first portion of said first transmitted data byte in a first storage location within the printer following the arrival of both said first and second clock signals within the printer; (i) transferring said second transmitted data byte with said second portion thereof having said first clock signal at said second logic level; (j) latching said first portion of said second transmitted data byte in a second storage location within the printer following the arrival of both said first and second clock signals within the printer, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the printer and can be reformed as said byte of printer data; and (k) repeatedly printing the character transferred and latched in steps (g)-(h) the number of times represented by said count number resulting from steps (b)-(e).

Claim 51

A method in a host computer system attached to a peripheral of transferring a byte of data between the host computer and the peripheral, the method comprising the steps of: (a) apportioning a byte of peripheral data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal; (b) transferring said first transmitted data byte with said second portion thereof having said first clock signal at said first logic level; (c) latching said first portion of said first transmitted data byte in a first storage location within the peripheral following the arrival of both said first and second clock signals within the peripheral; (d) transferring said second transmitted data byte with said second portion thereof having said first clock signal at said second logic level; and (e) latching said first portion of said second transmitted data byte in a second storage location within the peripheral following the arrival of both said first and second clock signals within the peripheral, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the peripheral and can be reformed as said byte of peripheral data.

Claim 52

A method in a host computer system attached to a peripheral of transferring a byte of data between the host computer and the peripheral, the method comprising the steps of: (a) apportioning a byte of peripheral data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal; (b) transferring said first transmitted data byte with said second portion thereof having said first clock signal at said first logic level; (c) latching said first portion of said first transmitted data byte in a first storage location within the peripheral following the arrival of both said first and second clock signals within the peripheral; (d) transferring said second transmitted data byte with said second portion thereof having said first clock signal at said second logic level; and (e) latching said first portion of said second transmitted data byte in a second storage location within the peripheral following the arrival of both said first and second clock signals within the peripheral, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the peripheral and can be reformed as said byte of peripheral data.

Claim 56

A method in a host computer system attached to a peripheral of transferring a byte of peripheral data between the host computer and the peripheral, the byte of peripheral data being apportioned into a first portion of first and second transmitted data bytes, the first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, the second clock signal being a logically inverted version of the first clock signal, the method comprising the steps of the method comprising the steps of: (a) transferring the first transmitted data byte with the second portion thereof having the first clock signal at the first logic level: (b) latching the first portion of the first transmitted data byte in a first storage location within the peripheral following the arrival of both the first and second clock signals within the peripheral; (c) transferring the second transmitted data byte with the second portion thereof having the first clock signal at the second logic level; and (d) latching the first portion of the second transmitted data byte in a second storage location within the peripheral following the arrival of both the first and second clock signals within the peripheral, whereby the first portions of the first and second transmitted data bytes are transmitted from the host computer to the peripheral and can be reformed as the byte of peripheral data.

Claim 57

A method in a host computer system attached to a peripheral of transferring a byte of peripheral data between the host computer and the peripheral, the byte of peripheral data being apportioned into a first portion of first and second transmitted data bytes, the first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, the second clock signal being a logically inverted version of the first clock signal, the method comprising the steps of the method comprising the steps of: (a) transferring the first transmitted data byte with the second portion thereof having the first clock signal at the first logic level: (b) latching the first portion of the first transmitted data byte in a first storage location within the peripheral following the arrival of both the first and second clock signals within the peripheral; (c) transferring the second transmitted data byte with the second portion thereof having the first clock signal at the second logic level; and (d) latching the first portion of the second transmitted data byte in a second storage location within the peripheral following the arrival of both the first and second clock signals within the peripheral, whereby the first portions of the first and second transmitted data bytes are transmitted from the host computer to the peripheral and can be reformed as the byte of peripheral data.

Claim 60

A method in a host computer system attached to a peripheral of transferring a byte of data between the host computer and the peripheral, the method comprising the steps of: (a) apportioning a byte of peripheral data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal; (b) transferring said first transmitted data byte with said second portion thereof having said first clock signal at said first logic level; (c) digitally filtering said first and second clock signals within the peripheral to generate first and second digitally filtered clock signals; (d) latching said first portion of said first transmitted data byte in a first storage location within the peripheral using said first and second digitally filtered clock signals; (e) transferring said second transmitted data byte with said second portion thereof having said first clock signal at said second logic level: (f) digitally filtering said first and second clock signals within the peripheral to generate said first and second digitally filtered clock signals; and (g) latching said first portion of said second transmitted data byte in a second storage location within the peripheral using said first and second digitally filtered clock signals, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the peripheral and can be reformed as said byte of peripheral data.

Claim 61

A method in a host computer system attached to a peripheral of transferring a byte of data between the host computer and the peripheral, the method comprising the steps of: (a) apportioning a byte of peripheral data into a first portion of first and second transmitted data bytes, said first and second transmitted data bytes each further including a second portion containing first and second clock signals each having first and second logic levels, said second clock signal being a logically inverted version of said first clock signal; (b) transferring said first transmitted data byte with said second portion thereof having said first clock signal at said first logic level; (c) digitally filtering said first and second clock signals within the peripheral to generate first and second digitally filtered clock signals; (d) latching said first portion of said first transmitted data byte in a first storage location within the peripheral using said first and second digitally filtered clock signals; (e) transferring said second transmitted data byte with said second portion thereof having said first clock signal at said second logic level: (f) digitally filtering said first and second clock signals within the peripheral to generate said first and second digitally filtered clock signals; and (g) latching said first portion of said second transmitted data byte in a second storage location within the peripheral using said first and second digitally filtered clock signals, whereby said first portions of said first and second transmitted data bytes are transmitted from the host computer to the peripheral and can be reformed as said byte of peripheral data.