Encoding/decoding circuit, and digital video system comprising the circuit

Claim 1

An encoding/decoding circuit having a first operating mode as an encoder for encoding successive blocks of a series of data words supplied thereto, the data words in each block being sequentially encoded in accordance with first and second error protection codes to thereby form code words in each of said codes for recording on a record carrier; said circuit also having a second operating mode as a decoder for decoding each of successive blocks of recorded code words recovered from the record carrier, each recovered block of code words being sequentially decoded in accordance with said first and second error protection codes in reverse order to thereby recover decoded data words; said circuit comprising: a first, a second and a third sub-circuit; said first sub-circuit comprising: a first encoder for receiving a block of a first series of code words which has already been formed by the second sub-circuit in accordance with the second error protection code, said first encoder encoding said block of supplied data words in accordance with the first error protection code to thereby derive a second series of code words, said first and second series of code words being for recording on the record carrier; and a first decoder for receiving from the record carrier a block of code words which has been recorded thereon and decoding said block in accordance with the first error protection code to thereby derive a block of partially decoded code words; said first sub-circuit having a first system clock frequency; said second sub-circuit comprising: a second encoder for also receiving a block of supplied data words and encoding in accordance with the second error protection code to form said first series of code words; and a second decoder for receiving said block of partially decoded code words and decoding in accordance with the second error protection code to thereby derive decoded data words, the decoded data words being data words from which the recorded block of code words was derived; said second sub-circuit having a second system clock frequency; said third sub-circuit comprising interface means for receiving the supplied data words at a data word clock frequency and outputting the supplied data words to be encoded by said second encoder; said interface means also receiving the decoded data words derived by said second decoder and outputting said decoded data words at said data word clock frequency; said third sub-circuit having a third system clock frequency; a frame memory for providing intermediate storage of (i) blocks of supplied data words outputted by said interface means, (ii) blocks of partially decoded code words produced by said first decoder from code words recorded on the record carrier, and (iii) blocks of decoded data words derived by said second decoder for supply to said interface means; switching means coupled to each of said sub-circuits and to said frame memory for providing cyclically multiplexed access to said frame memory by each of said sub-circuits; and control means for controlling said switching means so that said cyclically multiplexed access to said frame memory is at a frequency at least equal to the sum of said first, second and third system clock frequencies, whereby each of said sub-circuits is provided with cyclically multiplexed access to said frame memory at a frequency corresponding to the system clock frequency of the relevant sub-circuit.