Error detection and correction of a semiconductor memory device

Claim 2

A semiconductor memory comprising: a first PROM for storing first data; a second PROM for storing second data; an error correcting circuit, which when activated, corrects said first data with said second data and outputs corrected data, and which, when deactivated, outputs said first data uncorrected irrespective of whether or not said first data is in error; a control register for receiving control data, for storing said control data, for responding to said control data stored therein and for outputting, in response to said control data, a control signal to control said error correcting circuit, said control signal being either a valid control signal or an invalid control signal, such that said error correcting circuit is activated when said control register is outputting said valid control signal, and said error correcting circuit is deactivated when said control register is outputting said invalid control signal.

Claim 3

A semiconductor memory according to claim 1, wherein said control data includes data indicating when a debugging operation of a program stored in said first PROM is being executed, and, when a debugging operation is being performed,, said control register outputs, in response to said control data, said invalid control signal so that said error correcting circuit does not operate, and when said debugging operation is completed, said control register outputs, in response to said control data, said valid control signal so that said error correcting circuit operates to correct said first data with said second data.

Claim 4

A semiconductor memory comprising: a first PROM for storing first data; a second PROM for storing second data; an error correcting circuit for correcting said first data with said second data and outputting the corrected data when said error correcting circuit is activated, and outputting said first data uncorrected when said error correcting circuit is deactivated; a control register for receiving control data, for storing said control data, for responding to said control data stored therein and for outputting, in response to said control data, a control signal; a data bus, which includes at least one data bus terminal, commonly connected to said first PROM, said second PROM, said error correcting circuit, and said control register; an address bus, a first portion of said address bus being assigned to said first PROM and a second portion of said address bus being assigned to said second PROM; a control signal connection for supplying the control signal output by said control register to said error correcting circuit, the control signal being either a valid control signal or an invalid control signal, and the error correcting circuit being configured so that when said error correcting circuit receives the invalid control signal, said error detecting circuit is deactivated, and when said error detecting circuit receives the valid control signal, said error detecting circuit is activated.

Claim 5

A semiconductor memory comprising: a first PROM for storing first data; a second PROM for storing second data; an error correcting circuit for correcting said first data with said second data and outputting the corrected data when said error correcting circuit is activated, and outputting said first data uncorrected when said error correcting circuit is deactivated; a control register for receiving control data, for storing said control data, for responding to said control data stored therein and for outputting, in response to said control data, a control signal; a data bus, which includes at least one data bus terminal, commonly connected to said first PROM, said second PROM, said error correcting circuit, and said control register; an address bus, a first portion of said address bus being assigned to said first PROM and a second portion of said address bus being assigned to said second PROM; a control signal connection for supplying the control signal output by said control register to said error correcting circuit, the control signal being either a valid control signal or an invalid control signal, and the error correcting circuit being configured so that when said error correcting circuit receives the invalid control signal, said error detecting circuit is deactivated, and when said error detecting circuit receives the valid control signal, said error detecting circuit is activated.

Claim 6

A semiconductor memory as set forth in claim 3, wherein said control data includes data indicating when a debugging operation of a program stored in said first PROM is being executed, and, when a debugging operation is being performed, said control register outputs, in response to said control data, said invalid control signal so that said error correcting circuit does not operate, and when said debugging operation is completed, said control register outputs, in response to said control data, said valid control signal so that said error correcting circuit operates to correct said first data with said second data.