US5473548A
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US
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Apparatus for computing power consumption of MOS transistor logic function block
Assignee: Mitsubishi Electric Corp
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Filing: 1993-07-30
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Granted: 1995-12-05
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Expires: 2013-07-30
Abstract
Abstract Apparatus for computing power consumption in an MOS transistor logic function block include circuit information deriving unit for deriving circuit information appropriate for a logic function block of interest based on input and output varying signals to and from said logic function block, load capacitance data, and a net list, slew rate determining unit for determining an input slew rate based on information from said circuit information deriving unit, a memory section containing expressions for use in computation of power consumption caused by through-current, each expression corresponding to a different one of various types of logic function blocks and representing power consumption caused by through-current as a function of a slew rate and load capacitance, and power consumption determining unit for determining power consumption due to through-current by substituting the slew rate as determined by said slew rate determining unit and load capacitance data into the computation expression as read from said memory section.
Inventors
- 👤 Naoko Omori
- 👤 Michio Komoda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 22:58
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F2119/00; G06F2119/06
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
148 words
Apparatus for computing power consumption in an MOS transistor logic function block, comprising: circuit information deriving means for deriving circuit information appropriate for a logic function block of interest based on a plurality input and output varying signals to and from said logic function block and a net list; slew rate determining means for determining an input slew rate based on information from said circuit information deriving means; a memory section containing expressions for use in computation of power consumption caused by a through-current, each expression corresponding to a different one of various types of logic function blocks and representing power consumption caused by said through-current as a function of said input slew rate; and means for determining power consumption due to said through-current by substituting said input slew rate as determined by said slew rate determining means into a computation expression as read from said memory section.
Claim 2
Dependent Claim
148 words
Apparatus for computing power consumption in an MOS transistor logic function block, comprising: circuit information deriving means for deriving circuit information appropriate for a logic function block of interest based on a plurality input and output varying signals to and from said logic function block and a net list; slew rate determining means for determining an input slew rate based on information from said circuit information deriving means; a memory section containing expressions for use in computation of power consumption caused by a through-current, each expression corresponding to a different one of various types of logic function blocks and representing power consumption caused by said through-current as a function of said input slew rate; and means for determining power consumption due to said through-current by substituting said input slew rate as determined by said slew rate determining means into a computation expression as read from said memory section.
Claim 3
Dependent Claim
66 words
Apparatus for computing power consumption in an MOS transistor logic function block according to claim 1, further comprising: means for determining power consumption caused by a load capacitance; and means for summing the power consumption as determined by said means for determing power consumption due to said through-current and the power consumption as determined by said means for determing power consumption caused by said load capacitance.
Claim 4
Dependent Claim
61 words
Apparatus for computing power consumption in an MOS transistor logic function block according to claim 2, further comprising: means for multiplying a power consumption in an operation cycle of each logic function block by a number of operating cycles in unit time to obtain a plurality of results, and means for summing said plurality of results of respective logic function blocks.
Claim 5
Dependent Claim
173 words
Apparatus for computing power consumption in an MOS transistor logic function block, comprising: circuit information deriving means for deriving circuit information appropriate for a logic function block of interest based on a plurality of input and output varying signals to and from said logic function block, a plurality of load capacitance data, and a net list; slew rate determining means for determining an input slew rate based on information from said circuit information deriving means; a memory section containing a plurality of expressions for use in computation of power consumption caused by a through-current, each expression corresponding to a different one of various types of logic function blocks and representing power consumption caused by said through-current as a function of said input slew rate and said plurality of load capacitance data; and means for determining power consumption due to said through-current by substituting the said input slew rate as determined by said slew rate determining means and said plurality of load capacitance data into a computation expression as read from said memory section.
Claim 6
Dependent Claim
173 words
Apparatus for computing power consumption in an MOS transistor logic function block, comprising: circuit information deriving means for deriving circuit information appropriate for a logic function block of interest based on a plurality of input and output varying signals to and from said logic function block, a plurality of load capacitance data, and a net list; slew rate determining means for determining an input slew rate based on information from said circuit information deriving means; a memory section containing a plurality of expressions for use in computation of power consumption caused by a through-current, each expression corresponding to a different one of various types of logic function blocks and representing power consumption caused by said through-current as a function of said input slew rate and said plurality of load capacitance data; and means for determining power consumption due to said through-current by substituting the said input slew rate as determined by said slew rate determining means and said plurality of load capacitance data into a computation expression as read from said memory section.
Claim 7
Dependent Claim
66 words
Apparatus for computing power consumption in an MOS transistor logic function block according to claim 4, further comprising: means for determining power consumption caused by a load capacitance; and means for summing the power consumption as determined by said means for determining power consumption due to said through-current and the power consumption as determined by said means for determining power consumption caused by said load capacitance.
Claim 8
Dependent Claim
61 words
Apparatus for computing power consumption in an MOS transistor logic function block according to claim 5, further comprising: means for multiplying a power consumption in an operation cycle of each logic function block by a number of operating cycles in unit time to obtain a plurality of results, and means for summing said plurality of results of respective logic function blocks.
Claim 9
Independent Claim
203 words
A method for computing a total power consumption in a plurality of MOS transistor logic function blocks, comprising the steps of: deriving circuit information for each of said logic function blocks; said circuit information including a plurality of load capacitances, one load capacitance for each of said logic function blocks; said circuit information including a plurality of input signal changes, one input signal change for each logic function block; said circuit information including a plurality of output signal changes, one output signal change for each logic function block; determining an input slew rate for each of said logic function blocks; storing a plurality of formulas for computing a first plurality of power consumptions; a different one of each of said formulas associated with a different type of logic function block; said plurality of formulas being expressed as a function of said input slew rate; computing said first plurality of power consumptions; computing a second plurality of power consumptions; summing said first plurality of power consumptions to obtain a through-current power consumption; summing said second plurality of power consumptions to obtain a load capacitance power consumption; and summing said load capacitance power consumption and said through-current power consumption to obtain a total power consumption.
Claim 10
Independent Claim
203 words
A method for computing a total power consumption in a plurality of MOS transistor logic function blocks, comprising the steps of: deriving circuit information for each of said logic function blocks; said circuit information including a plurality of load capacitances, one load capacitance for each of said logic function blocks; said circuit information including a plurality of input signal changes, one input signal change for each logic function block; said circuit information including a plurality of output signal changes, one output signal change for each logic function block; determining an input slew rate for each of said logic function blocks; storing a plurality of formulas for computing a first plurality of power consumptions; a different one of each of said formulas associated with a different type of logic function block; said plurality of formulas being expressed as a function of said input slew rate; computing said first plurality of power consumptions; computing a second plurality of power consumptions; summing said first plurality of power consumptions to obtain a through-current power consumption; summing said second plurality of power consumptions to obtain a load capacitance power consumption; and summing said load capacitance power consumption and said through-current power consumption to obtain a total power consumption.
Claim 11
Independent Claim
207 words
A method for computing a total power consumption in a plurality of MOS transistor logic function blocks, comprising the steps of: deriving circuit information for each of said logic function blocks; said circuit information including a plurality of load capacitances, one load capacitance for each of said logic function blocks; said circuit information including a plurality of input signal changes, one input signal change for each logic function block; said circuit information including a plurality of output signal changes, one output signal change for each logic function block; determining an input slew rate for each of said logic function blocks; storing a plurality of formulas for computing a first plurality of power consumptions; a different one of each of said formulas associated with a different type of logic function block; said plurality of formulas being expressed as a function of said input slew rate and said load capacitance; computing said first plurality of power consumptions; computing a second plurality of power consumptions; summing said first plurality of power consumptions to obtain a through-current power consumption; summing said second plurality of power consumptions to obtain a load capacitance power consumption; and summing said load capacitance power consumption and said through-current power consumption to obtain a total power consumption.
Claim 12
Independent Claim
207 words
A method for computing a total power consumption in a plurality of MOS transistor logic function blocks, comprising the steps of: deriving circuit information for each of said logic function blocks; said circuit information including a plurality of load capacitances, one load capacitance for each of said logic function blocks; said circuit information including a plurality of input signal changes, one input signal change for each logic function block; said circuit information including a plurality of output signal changes, one output signal change for each logic function block; determining an input slew rate for each of said logic function blocks; storing a plurality of formulas for computing a first plurality of power consumptions; a different one of each of said formulas associated with a different type of logic function block; said plurality of formulas being expressed as a function of said input slew rate and said load capacitance; computing said first plurality of power consumptions; computing a second plurality of power consumptions; summing said first plurality of power consumptions to obtain a through-current power consumption; summing said second plurality of power consumptions to obtain a load capacitance power consumption; and summing said load capacitance power consumption and said through-current power consumption to obtain a total power consumption.
Claim 13
Dependent Claim
84 words
Apparatus for measuring power consumption of a logic device comprising: means for determining an input slew rate of an input signal to said logic device; means, responsive to said slew rate, for calculating a first power consumption resulting from a through-current of said logic device; means for calculating a second power consumption resulting from a charging current of said logic device; and means for summing said first power consumption and said second power consumption to provide a total power consumption of said logic device.
Claim 14
Dependent Claim
84 words
Apparatus for measuring power consumption of a logic device comprising: means for determining an input slew rate of an input signal to said logic device; means, responsive to said slew rate, for calculating a first power consumption resulting from a through-current of said logic device; means for calculating a second power consumption resulting from a charging current of said logic device; and means for summing said first power consumption and said second power consumption to provide a total power consumption of said logic device.
Claim 15
Dependent Claim
39 words
The apparatus of claim 9, wherein said means, responsive to said slew rate, includes means for applying a formula W.sub.P =b+mt, where W p is said power consumption, t is said slew rate, and b and m are constants.
Claim 16
Dependent Claim
111 words
Apparatus for measuring power consumption of a logic device comprising: means for determining an input slew rate of an input signal to said logic device; first means, responsive to said slew rate, for calculating a first power consumption resulting from a through-current of said logic device; second means, responsive to said slew rate, for calculating a second power consumption resulting from said through-current of said logic device; third means for calculating a third power consumption resulting from a charging current of said logic device; and means, for summing said first power consumption, said second power consumption, and said third power consumption, to provide a total power consumption of said logic device.
Claim 17
Dependent Claim
111 words
Apparatus for measuring power consumption of a logic device comprising: means for determining an input slew rate of an input signal to said logic device; first means, responsive to said slew rate, for calculating a first power consumption resulting from a through-current of said logic device; second means, responsive to said slew rate, for calculating a second power consumption resulting from said through-current of said logic device; third means for calculating a third power consumption resulting from a charging current of said logic device; and means, for summing said first power consumption, said second power consumption, and said third power consumption, to provide a total power consumption of said logic device.
Claim 18
Dependent Claim
43 words
Apparatus according to claim 11, wherein said first and second means include means for applying a formula W.sub.P =α+βt-γtc, where W P is a power consumption, t is said slew rate, c is a load capacitance, and α, β, and γ are constants.
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| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
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