US5473576A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random access memory device with low-power consumption column selector
Assignee: NEC Electronics Corp
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Filing: 1994-07-27
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Granted: 1995-12-05
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Expires: 2014-07-27
Abstract
Abstract A column selector of a dynamic random access memory device is implemented by a plurality of switching circuits for transferring a potential difference from a sense amplifier to a shared data line pair, and one of the switching circuits selectively discharge the data lines of the pair to a ground voltage line for transferring the potential difference to the shared data line pair, wherein a potential control circuit is coupled between the switching circuits and the ground voltage line for decreasing the current flowing from the data line to the ground voltage line after production of an output data signal, thereby decreasing the current consumption.
Inventors
- 👤 Yoshinori Matsui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C11/4093; G11C7/00; G11C7/10; G11C7/1048
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
312 words
A semiconductor memory device comprising: a) a plurality of addressable memory cells for storing data bits; b) a plurality of pairs of first data lines selectively coupled to said plurality of addressable memory cells; c) a first addressing system for selectively connecting said plurality of addressable memory cells to said plurality of pairs of first data lines; d) second data lines paired with each other; e) a charging circuit coupled to said second data lines for supplying current thereto; f) a discharging line for discharging said current; g) a second addressing system having a plurality of switching circuits coupled in parallel between said second data lines and said discharging line, one of said plurality of switching circuits being responsive to a data bit on one of said plurality of pairs of first data lines for selectively connecting said second data lines to said discharging line, thereby transferring said data bit to said second data lines in the form of potential difference; h) an interface responsive to said data bit on said second data lines for producing a data signal; and i) a current control means operative to increase the current flowing from said discharging line to a voltage source for enlarging the potential difference between said second data lines before said interface produces said data signal and to decrease said current after completion of the production of said data signal, said current control means including i-1) a diode coupled between said discharging line and said voltage source; and i-2) a switching transistor coupled between said discharging line and said voltage source in parallel to said diode, and responsive to a control signal so as to provide a current path before said interface produces said data signal, said control signal being changed to an inactive level after said completion of the production of said data signal so that said switching transistor turns off.
Claim 2
Dependent Claim
312 words
A semiconductor memory device comprising: a) a plurality of addressable memory cells for storing data bits; b) a plurality of pairs of first data lines selectively coupled to said plurality of addressable memory cells; c) a first addressing system for selectively connecting said plurality of addressable memory cells to said plurality of pairs of first data lines; d) second data lines paired with each other; e) a charging circuit coupled to said second data lines for supplying current thereto; f) a discharging line for discharging said current; g) a second addressing system having a plurality of switching circuits coupled in parallel between said second data lines and said discharging line, one of said plurality of switching circuits being responsive to a data bit on one of said plurality of pairs of first data lines for selectively connecting said second data lines to said discharging line, thereby transferring said data bit to said second data lines in the form of potential difference; h) an interface responsive to said data bit on said second data lines for producing a data signal; and i) a current control means operative to increase the current flowing from said discharging line to a voltage source for enlarging the potential difference between said second data lines before said interface produces said data signal and to decrease said current after completion of the production of said data signal, said current control means including i-1) a diode coupled between said discharging line and said voltage source; and i-2) a switching transistor coupled between said discharging line and said voltage source in parallel to said diode, and responsive to a control signal so as to provide a current path before said interface produces said data signal, said control signal being changed to an inactive level after said completion of the production of said data signal so that said switching transistor turns off.
Claim 3
Dependent Claim
48 words
The semiconductor memory device as set forth in claim 1, in which said diode is implemented by a field effect transistor having a source-to-drain path coupled between said discharging line and said voltage source, a gate electrode of said field effect transistor being coupled to said discharging line.
Claim 4
Dependent Claim
34 words
The semiconductor memory device as set forth in claim 1, in which said plurality of addressable memory cells are a random access type for storing the data bits in the form of electric charges.
Claim 5
Dependent Claim
49 words
The semiconductor memory device as set forth in claim 3, further comprising j) a plurality of sense amplifier circuits respectively associated with said plurality of pairs of first data lines for rapidly developing potential differences indicative of the data bits on said plurality of pairs of first data lines.
Claim 6
Dependent Claim
198 words
The semiconductor memory device as set forth in claim 4, in which each of said plurality of pairs of first data lines is split into a first section coupled to first memory cells selected from said plurality of addressable memory cells, a second section coupled to second memory cells selected from said plurality of addressable memory cells and a third section provided between said first section and said second section and coupled to one of said sense amplifier circuits and one of said switching circuits, said semiconductor memory device further comprising: k) a first transfer gate array coupled between the first sections of said plurality of pairs of first data lines and the third sections of said plurality of pairs of first data lines, and responsive to a first gate control signal for electrically connecting said first sections to said third sections; and l) a second transfer gate array coupled between the second sections and said third sections, and responsive to a second gate control signal for electrically connecting second sections to said third sections, one of said first gate control signal and said second gate control signal being changed to an active level in each data access.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-04 | 2003-06-05 | 2003-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-04 | 2007-06-05 | 2007-12-05 | $7700.00 | Window Closed / Lapsed |