US5475846A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for processing PCMCIA interrupt requests
Assignee: Databook Inc
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Filing: 1993-08-11
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Granted: 1995-12-12
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Expires: 2013-08-11
Abstract
Abstract An apparatus to permit the sharing of interrupts between resident devices and removable PCMCIA peripherals overcomes a deficiency in the PCMCIA standards. By permitting interrupt sharing, the apparatus allows standard application software, which assumes the interrupt sharing capability of standard built-in peripherals to operate with PCMCIA cards. The invention is particularly suited to serial communication ports, where interrupts are routinely shared. An interface component 20 is coupled to an interrupt controller 12. A serial port COM1 is connected to a host interrupt IRQ4, which is shared by a PCMCIA card serial port 22, configured as COM3, through the interface controller 20. Through the use of an open-drain output and a conversion in the controller 20 of the level mode interrupt from the PCMCIA card to a low-going pulse of sufficient voltage swing and duration, the host interrupt is shared between the permanently installed COM1 and the removable COM3 serial ports.
Inventors
- 👤 Terrill M. Moore
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:31
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
265 words
A computer system comprising: a microprocessor; an interrupt controller coupled to said microprocessor, said interrupt controller having at least a first interrupt request input; a pull-up resistor coupled between a power source and said first interrupt request input; first serial port means having a first output coupled to said first interrupt request input and a first peripheral port input coupled to a first peripheral device, said first serial port means when enabled outputting a first non-interrupt state on said first output until a first interrupt request is received from said first peripheral device and then outputting a first interrupt state on said first output and said first serial port means when disabled outputting a first high impedance state on said first output; and second serial port means having a second output coupled to an interface component and a second peripheral port input coupled to a second peripheral device, said second serial port means when enabled outputting a second non-interrupt state on said second output until a second interrupt request is received from said second peripheral device and then outputting a second interrupt state on said second output and said second serial port when disabled outputting a second high impedance state on said second output; and said interface component having an interface output coupled to said first interrupt request input, said interface component outputting a third high impedance state when said interface output receives said second non-interrupt state or said second high impedance state and outputting a third interrupt state when said interface component receives a second interrupt state and said first serial port is disabled.
Claim 2
Dependent Claim
265 words
A computer system comprising: a microprocessor; an interrupt controller coupled to said microprocessor, said interrupt controller having at least a first interrupt request input; a pull-up resistor coupled between a power source and said first interrupt request input; first serial port means having a first output coupled to said first interrupt request input and a first peripheral port input coupled to a first peripheral device, said first serial port means when enabled outputting a first non-interrupt state on said first output until a first interrupt request is received from said first peripheral device and then outputting a first interrupt state on said first output and said first serial port means when disabled outputting a first high impedance state on said first output; and second serial port means having a second output coupled to an interface component and a second peripheral port input coupled to a second peripheral device, said second serial port means when enabled outputting a second non-interrupt state on said second output until a second interrupt request is received from said second peripheral device and then outputting a second interrupt state on said second output and said second serial port when disabled outputting a second high impedance state on said second output; and said interface component having an interface output coupled to said first interrupt request input, said interface component outputting a third high impedance state when said interface output receives said second non-interrupt state or said second high impedance state and outputting a third interrupt state when said interface component receives a second interrupt state and said first serial port is disabled.
Claim 3
Dependent Claim
94 words
The computer system according to claim 1 wherein said first serial port means further comprises a first tristate buffer having a first buffer output coupled to said first interrupt request input and a first buffer input coupled to a first serial port, said first serial port coupled to said first peripheral device and said second serial port means comprises a second tristate buffer having a second buffer output coupled to said interface component and a second buffer input coupled to a second serial port, said second serial port coupled to said second peripheral device.
Claim 4
Dependent Claim
15 words
The computer system according to claim 2 wherein said interface output is an open-drain output.
Claim 5
Dependent Claim
27 words
The computer system according to claim 2 wherein said second peripheral device is in compliance with Personal Computer Memory Card International Association/Japanese Electronic Industry Development Association standards.
Claim 6
Dependent Claim
36 words
The computer system according to claim 2 further comprising a bus coupled to said interface component and said first serial port, said bus providing a control signal which either enables or disables said first tristate buffer.
Claim 7
Dependent Claim
15 words
The computer system according to claim 1 wherein said interface output is an open-drain output.
Claim 8
Dependent Claim
27 words
The computer system according to claim 6 wherein said second peripheral device is in compliance with Personal Computer Memory Card International Association/Japanese Electronic Industry Development Association standards.
Claim 9
Dependent Claim
36 words
The computer system according to claim 6 further comprising a bus coupled to said interface component and said first serial port, said bus providing a control signal which either enables or disables said first tristate buffer.
Claim 10
Dependent Claim
38 words
The computer system according to claim 1 further comprising a bus coupled to said interface component and said first serial port means, said bus providing a control signal which either enables or disables said first serial port means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-11 | 1999-06-12 | 1999-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-11 | 2003-06-12 | 2003-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-11 | 2007-06-12 | 2007-12-12 | $7700.00 | Window Closed / Lapsed |