US5475856A — Dynamic multi-mode parallel processing array

Claim 1

Independent Claim 381 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction; wherein a controlling processor of a group of processors fetches instructions, and wherein other processors in the group latch into their instruction registers each instruction as the controlling processor fetches it, such that at the end of the instruction fetch all other processors have in their instruction register the fetched instruction; and wherein the instruction set includes instructions which modify a processor's program counter to function as a base register, including one or more of the following instructions: a "Jump" instruction which when executed in a processor operating in SIMD mode sets the processor's program counter to a value provide with the jump instruction; and a "Load Immediate" instruction which when executed in a processor operating in SIMD mode loads a register with the contents of the processors' local memory, at the address specified by the processor's program counter and then increments the program counter.

Claim 2

Dependent Claim 381 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction; wherein a controlling processor of a group of processors fetches instructions, and wherein other processors in the group latch into their instruction registers each instruction as the controlling processor fetches it, such that at the end of the instruction fetch all other processors have in their instruction register the fetched instruction; and wherein the instruction set includes instructions which modify a processor's program counter to function as a base register, including one or more of the following instructions: a "Jump" instruction which when executed in a processor operating in SIMD mode sets the processor's program counter to a value provide with the jump instruction; and a "Load Immediate" instruction which when executed in a processor operating in SIMD mode loads a register with the contents of the processors' local memory, at the address specified by the processor's program counter and then increments the program counter.

Claim 3

Dependent Claim 326 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction; wherein a group of processors operating in SIMD mode switch to MIMD mode when the controlling processor provides each processor in the group with the switch mode instruction whereby each processor begins fetching instructions from its local memory; and wherein the processors can communicate with each other using a load instruction to send and a store instruction to receive, said instructions containing an address which is used as a processor address on the interconnection path of the processor to communicate with, wherein the processor stalls until the communication takes place.

Claim 4

Dependent Claim 326 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction; wherein a group of processors operating in SIMD mode switch to MIMD mode when the controlling processor provides each processor in the group with the switch mode instruction whereby each processor begins fetching instructions from its local memory; and wherein the processors can communicate with each other using a load instruction to send and a store instruction to receive, said instructions containing an address which is used as a processor address on the interconnection path of the processor to communicate with, wherein the processor stalls until the communication takes place.

Claim 5

Dependent Claim 342 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having an control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction; wherein a group of processors operating in SIMD mode switch to MIMD mode when the controlling processor provides each processor in the group with the switch mode instruction whereby each processor begins fetching instructions from its local memory; and wherein a switch mode instruction executed by a first processor causes the first processor to stall and use an address provided by the switch mode instruction as a key back to the controlling processor, the controller processor can then execute a switch mode instruction with an "address" which matches the key, and causes the first processor to leave the stall and resume tracking the controlling processor's instructions.

Claim 6

Dependent Claim 342 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having an control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction; wherein a group of processors operating in SIMD mode switch to MIMD mode when the controlling processor provides each processor in the group with the switch mode instruction whereby each processor begins fetching instructions from its local memory; and wherein a switch mode instruction executed by a first processor causes the first processor to stall and use an address provided by the switch mode instruction as a key back to the controlling processor, the controller processor can then execute a switch mode instruction with an "address" which matches the key, and causes the first processor to leave the stall and resume tracking the controlling processor's instructions.

Claim 7

Dependent Claim 315 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit able to decode and execute instructions of an instruction set, a data flow unit and a local memory, each control unit having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction; wherein a group of processors operating in SIMD mode switch to MIMD mode when the controlling processor provides each processor in the group with the switch mode instruction whereby each processor begins fetching instructions from its local memory; and wherein a variable subset of processors operating in MIMD mode execute switch mode instructions that cause the variable subset of processors to operate in SIMD mode while those processors that are not part of the variable subset continue operating in MIMD mode.

Claim 8

Dependent Claim 315 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit able to decode and execute instructions of an instruction set, a data flow unit and a local memory, each control unit having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction; wherein a group of processors operating in SIMD mode switch to MIMD mode when the controlling processor provides each processor in the group with the switch mode instruction whereby each processor begins fetching instructions from its local memory; and wherein a variable subset of processors operating in MIMD mode execute switch mode instructions that cause the variable subset of processors to operate in SIMD mode while those processors that are not part of the variable subset continue operating in MIMD mode.

Claim 9

Dependent Claim 32 words

The array according to claim 4 wherein the variable subset of processors return to MIMD mode when the controlling processor provides each processor in the variable subset with the switch mode instruction.

Claim 10

Dependent Claim 315 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction; and wherein the instruction set provides instructions where all memory references for data are performed via LOAD and STORE instructions, and where addressing for data accesses is a base plus displacement, and where addition and index register updates are applied after a memory operation has begun, as a post address update; and wherein all instructions that perform computational operations are register to register, and said processors execute instructions in one or more execution cycles without need of memory references.

Claim 11

Dependent Claim 315 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction; and wherein the instruction set provides instructions where all memory references for data are performed via LOAD and STORE instructions, and where addressing for data accesses is a base plus displacement, and where addition and index register updates are applied after a memory operation has begun, as a post address update; and wherein all instructions that perform computational operations are register to register, and said processors execute instructions in one or more execution cycles without need of memory references.

Claim 12

Dependent Claim 321 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction wherein a controlling processor of a group of processors fetches instructions, and wherein other processors in the group latch into their instruction registers each instruction as the controlling processor fetches it, such that at the end of the instruction fetch all other processors have in their instruction register the fetched instruction; and wherein after latching the fetched instruction each processor looks at its PMB and the PET obtained from the fetched instruction to determine whether to execute the fetched instruction, executing the fetched instruction accordingly.

Claim 13

Dependent Claim 321 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction wherein a controlling processor of a group of processors fetches instructions, and wherein other processors in the group latch into their instruction registers each instruction as the controlling processor fetches it, such that at the end of the instruction fetch all other processors have in their instruction register the fetched instruction; and wherein after latching the fetched instruction each processor looks at its PMB and the PET obtained from the fetched instruction to determine whether to execute the fetched instruction, executing the fetched instruction accordingly.

Claim 14

Dependent Claim 25 words

The array according to claim 7 wherein while the processors are decoding and executing the fetched instruction the controlling processor begins fetching a next instruction.

Claim 15

Dependent Claim 31 words

The array according to claim 8 wherein the controlling processor of a group of processors fetches another instruction all processors in SIMD mode capture the memory reference in their instruction registers.

Claim 16

Dependent Claim 262 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically on an instruction-by, instruction basis; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction; and wherein the PMB indicates SIMD and MIMD modes and the PET indicates local and array operations of the associated processor.

Claim 17

Dependent Claim 262 words

A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically on an instruction-by, instruction basis; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction; and wherein the PMB indicates SIMD and MIMD modes and the PET indicates local and array operations of the associated processor.

Claim 18

Dependent Claim 34 words

The array according to claim 10 wherein when a group of processors are operating in SIMD mode, the program counters provide a base register function in the processors receiving instructions from the controlling processor.

Claim 19

Dependent Claim 35 words

The array according to claim 10 wherein when a group of processors are operating in SIMD mode, the condition code register provide a local enable function in the processors receiving instructions from the controlling processor.

Claim 20

Dependent Claim 23 words

The array according to claim 10 wherein there is provided a plurality of groups, with each group dynamically switching between modes of operation.

Claim 21

Dependent Claim 16 words

The array according to claim 10 wherein the interconnection path is a dynamic switching connection network.

Claim 22

Dependent Claim 30 words

The array according to claim 10 wherein the interconnection path provides a broadcast path between the instructions registers of each processor in a group of processors executing in SIMD mode.

Claim 23

Dependent Claim 34 words

The array according to claim 10 wherein the interconnection path is a multi-stage interconnection network that provides a broadcast path to the instruction registers of a group of processors operating in a SIMD mode.

Claim 24

Dependent Claim 22 words

The array according to claim 10 wherein a switch mode instruction provides a value to load into the program counter when executed.

Claim 25

Dependent Claim 19 words

The array according to claim 10 wherein the switch mode instruction does not change the program counter when executed.

Claim 26

Dependent Claim 44 words

The array according to claim 10 wherein a group of processors operating in SIMD mode switch to MIMD mode when the controlling processor provides each processor in the group with the switch mode instruction whereby each processor begins fetching instructions from its local memory.

Claim 27

Dependent Claim 53 words

The array according to claim 10 wherein the interconnection path is utilized to pass broadcast messages and to interconnect a variety of subsets of processors within a group of processors, such that the processors may implement on a selective basis both SIMD and MIMD operations, some processors running SIMD and others running MIMD.

Claim 28

Dependent Claim 68 words

The array according to claim 10 wherein is included for processor interconnection a dynamic switching multi-stage network, wherein without blocking via alternative path selection processors can be set up as part of an interconnected system permitting selection of various groups of processors on the network which have desirable resources, and use them to run programs which can take advantage of the SIMD and MIMD needs of the application.

Claim 29

Dependent Claim 33 words

The array according to claim 10 wherein the controlling processor is dynamically rotated through a group of processors so that each processor is configured as the controlling processor for one or more instructions.

Claim 30

Dependent Claim 38 words

The array according to claim 10 wherein the instructions registers of processors are interconnected via an asynchronous network enabling a controlling processor to pass instructions through the interconnection network to other processor instruction registers coupled via said network.

Claim 31

Dependent Claim 21 words

The array according to claim 10 wherein each processor is provided with a port through which passes the switch mode instruction.

Claim 32

Dependent Claim 36 words

The array according to claim 10 wherein the controlling processor can switch to SISD mode permitting a programmer or compiler to build a program for the array which uses any one or all modes of parallelism.

Claim 33

Dependent Claim 27 words

The array according to claim 10 wherein the interconnection path is a dynamic multi-stage two sided switching network enabling point to point coupling of processors without blocking.

Claim 34

Dependent Claim 27 words

The array according to claim 26 wherein the multi-stage interconnection network provides broadcast paths to the instruction registers of a group of processors operating in SIMD mode.

Claim 35

Dependent Claim 28 words

The array according to claim 10 wherein a multi-stage interconnection network provides an alternative path between the instruction registers of a group of processors operating in SIMD mode.

Claim 36

Dependent Claim 27 words

The array according to claim 28 wherein the multi-stage interconnection network a dynamic multi-stage two sided switching network enabling point to point coupling of processors without blocking.

Claim 37

Dependent Claim 57 words

The may according to claim 10 wherein a controlling processor of a group of processors fetches instructions, and wherein other processors in the group latch into their instruction registers each instruction as the controlling processor fetches it, such that at the end of the instruction fetch all other processors have in their instruction register the fetched instruction.

Claim 38

Dependent Claim 22 words

The array according to claim 30 wherein execution of SIMD mode instructions proceeds with the program counter used as a base register.

Claim 39

Dependent Claim 42 words

The array according to claim 30 wherein the instruction set includes instructions which when executed in a processor operating in SIMD mode uses the program counter as a base register, the instruction including a Load immediate instruction and a store immediate instruction.

Claim 40

Dependent Claim 16 words

The array according to claim 10 wherein each processor is a reduced instruction set computer (RISC).

Claim 41

Dependent Claim 17 words

The array according to claim 33 wherein the interconnection path is provided by an ALLNODE interconnection network.

Claim 42

Dependent Claim 54 words

The array according to claim 10 including: a first group of processors operating in SIMD mode having a first controlling processor providing instructions for said first group over the interconnection path; and a second group operating in SIMD mode having a second controlling processor providing instructions for the second group over the interconnection path.

Claim 43

Dependent Claim 32 words

The array according to claim 35 wherein the first controlling processor provides the switch mode instruction to the first group of processors causing the first group of processors to enter MIMD mode.

Claim 44

Dependent Claim 32 words

The array according to claim 36 wherein the second controlling processor provides the switch mode instruction to the second group of processors causing the second group of processors to enter MIMD mode.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1998-12-11	1999-06-12	1999-12-12	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2002-12-11	2003-06-12	2003-12-12	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2006-12-11	2007-06-12	2007-12-12	$7700.00	Window Closed / Lapsed

Dynamic multi-mode parallel processing array

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