Three-dimensional multichip package

Claim 1

A three-dimensional multichip array package having a master integrated circuit semiconductor device supporting and interconnected with a densely stacked array of subordinate integrated circuit semiconductor devices comprising: a base semiconductor substrate provided with interconnected integrated circuit elements, an inner peripheral row of contact pads electrically connected to said circuit elements, and an outer peripheral row of terminal pads electrically connected to said contact pads, said base substrate constituting a master semiconductor device; a plurality of subordinate semiconductor substrates, each provided with interconnected integrated circuit elements, a peripheral row of contact pads electrically connected to said circuit elements, said row of contact pads arranged in a pattern that matches the pattern of the contact pads on said master semiconductor substrate, said subordinate semiconductor substrate constituting subordinate semiconductor devices; an insulating layer of organic material on the surfaces of said base substrate and said subordinate substrates; central openings through each of said contact pads of said subordinate semiconductor devices; a dielectric coating on the walls of said central openings that extend up to but not covering the edges of said contact pads; said subordinate semiconductor devices stacked to form an array with said central openings in registry, said array of devices supported on said master semiconductor device with said central openings in registry with said contact pads of said master semiconductor device; and an electrically conductive material within said central openings that established electrical contact between said contact pads of said subordinate semiconductor devices and said contact pads of said master semiconductor devices.