Methods for manufacturing low leakage current offset-gate thin film transistor

Claim 1

A method of manufacturing thin film transistors, comprising the steps of: a) forming a first thin silicon film on an insulation substrate; b) forming two patterns by selectively etching said first thin silicon film; c) disposing a second thin silicon film on said substrate, with at least a portion of said second thin silicon film being disposed between said two patterns and connecting said two patterns; d) forming, in turn, a gate insulation layer and an electrically conductive film on said two patterns and said second thin silicon film; e) forming a gate electrode by selectively etching said electrically conductive film; f) forming an insulation film on side walls of said gate electrode; and g) forming a source region and a drain region self-aligned to said gate electrode and said insulation film on said side walls by adding impurities to said two patterns and portions of said second thin silicon film with said gate electrode and said insulation film on said side walls as a mask; wherein said gate electrode does not overlap said source and drain areas and is laterally offset from said source and drain areas.

Claim 2

A method of manufacturing thin film transistors, comprising the steps of: a) forming a first thin silicon film on an insulation substrate; b) forming two patterns by selectively etching said first thin silicon film; c) disposing a second thin silicon film on said substrate, with at least a portion of said second thin silicon film being disposed between said two patterns and connecting said two patterns; d) forming, in turn, a gate insulation layer and an electrically conductive film on said two patterns and said second thin silicon film; e) forming a gate electrode by selectively etching said electrically conductive film; f) forming an insulation film on side walls of said gate electrode; and g) forming a source region and a drain region self-aligned to said gate electrode and said insulation film on said side walls by adding impurities to said two patterns and portions of said second thin silicon film with said gate electrode and said insulation film on said side walls as a mask; wherein said gate electrode does not overlap said source and drain areas and is laterally offset from said source and drain areas.

Claim 4

A method of manufacturing thin film transistors on an insulation substrate, comprising the steps of: a) forming a first thin silicon film on an insulation substrate; b) forming two patterns by selectively etching said first thin silicon film; c) disposing a second thin silicon film on said substrate, with: at least a portion of said second thin silicon film being disposed between said two patterns and connecting said two patterns; d) forming, in turn, a gate insulating layer and an electrically conductive film on said two patterns and said second thin silicon film; e) forming a gate electrode by selectively etching said electrically conductive film; f) forming an insulation layer over said gate electrode; g) etching said insulation layer, formed on said gate electrode, by anisotropic etching in such a manner that a portion of said insulation layer remains on the side walls of said gate electrode and form sidewalls of said gate electrode; and h) forming a source region and a drain region self-aligned to said gate electrode and said sidewalls by adding impurities to said two patterns and portions of said second thin silicon film with said gate electrode and said sidewalls as a mask; wherein said gate electrode does not overlap said source and drain areas and is laterally offset from said source and said drain areas.

Claim 5

A method of manufacturing thin film transistors on an insulation substrate, comprising the steps of: a) forming a first thin silicon film on an insulation substrate; b) forming two patterns by selectively etching said first thin silicon film; c) disposing a second thin silicon film on said substrate, with: at least a portion of said second thin silicon film being disposed between said two patterns and connecting said two patterns; d) forming, in turn, a gate insulating layer and an electrically conductive film on said two patterns and said second thin silicon film; e) forming a gate electrode by selectively etching said electrically conductive film; f) forming an insulation layer over said gate electrode; g) etching said insulation layer, formed on said gate electrode, by anisotropic etching in such a manner that a portion of said insulation layer remains on the side walls of said gate electrode and form sidewalls of said gate electrode; and h) forming a source region and a drain region self-aligned to said gate electrode and said sidewalls by adding impurities to said two patterns and portions of said second thin silicon film with said gate electrode and said sidewalls as a mask; wherein said gate electrode does not overlap said source and drain areas and is laterally offset from said source and said drain areas.

Claim 6

A method of manufacturing a thin film transistor, having a source region, a drain region and a gate electrode, in which the gate electrode does not overlap the source region and the drain region, comprising the steps of: a) forming a first thin silicon film on an insulating substrate; b) forming two patterns by selectively etching said first thin film; c) disposing a second thin silicon film on said substrate, with at least a portion of said second thin silicon film being disposed between said two patterns and connecting said two patterns; d) forming in turn, a gate insulation layer an electrically conductive film, and a first insulating layer on said two patterns and said second thin silicon film; e) forming an insulation pattern by selectively etching said first insulating layer; f) forming a gate electrode by selectively etching said electrically conductive film with said insulation pattern as a mask; g) forming a second insulating layer over said insulation pattern and said gate electrode; h) etching said second insulating layer by anisotropic etching in such a manner that a portion of said second insulating layer remains on the side walls of said gate electrode and said insulation pattern and form the sidewalls of said gate electrode and said insulation pattern; and i) forming a source region and a drain region self-aligned to said gate electrode, said insulation pattern and said sidewalls by adding impurities to said two patterns and portions of said second thin silicon film with said gate electrode, said insulation pattern and said sidewalls as a mask; wherein said gate electrode does not overlap said source and drain areas and is laterally offset from said source and drain areas.

Claim 7

A method of manufacturing a thin film transistor, having a source region, a drain region and a gate electrode, in which the gate electrode does not overlap the source region and the drain region, comprising the steps of: a) forming a first thin silicon film on an insulating substrate; b) forming two patterns by selectively etching said first thin film; c) disposing a second thin silicon film on said substrate, with at least a portion of said second thin silicon film being disposed between said two patterns and connecting said two patterns; d) forming in turn, a gate insulation layer an electrically conductive film, and a first insulating layer on said two patterns and said second thin silicon film; e) forming an insulation pattern by selectively etching said first insulating layer; f) forming a gate electrode by selectively etching said electrically conductive film with said insulation pattern as a mask; g) forming a second insulating layer over said insulation pattern and said gate electrode; h) etching said second insulating layer by anisotropic etching in such a manner that a portion of said second insulating layer remains on the side walls of said gate electrode and said insulation pattern and form the sidewalls of said gate electrode and said insulation pattern; and i) forming a source region and a drain region self-aligned to said gate electrode, said insulation pattern and said sidewalls by adding impurities to said two patterns and portions of said second thin silicon film with said gate electrode, said insulation pattern and said sidewalls as a mask; wherein said gate electrode does not overlap said source and drain areas and is laterally offset from said source and drain areas.

Claim 8

A method of manufacturing a thin film transistor having a source region, a drain region and a gate electrode, comprising the steps of: a) forming a thin silicon film on an insulating substrate; b) forming, in turn, a gate insulation layer and a gate electrode on said first thin silicon film; c) forming an insulation layer on top of said gate electrode and said gate insulation layer; d) selectively etching said insulation layer and said gate insulation layer so that a portion of said thin silicon film on each side of said gate electrode is exposed as an exposed portion; and e) forming a source region and a drain region by depositing a doped silicon layer on and covering each said exposed portion of said first thin silicon film, wherein said gate electrode does not overlap said source region and drain region.

Claim 9

A method of manufacturing a thin film transistor having a source region, a drain region and a gate electrode, comprising the steps of: a) forming a thin silicon film on an insulating substrate; b) forming, in turn, a gate insulation layer and a gate electrode on said first thin silicon film; c) forming an insulation layer on top of said gate electrode and said gate insulation layer; d) selectively etching said insulation layer and said gate insulation layer so that a portion of said thin silicon film on each side of said gate electrode is exposed as an exposed portion; and e) forming a source region and a drain region by depositing a doped silicon layer on and covering each said exposed portion of said first thin silicon film, wherein said gate electrode does not overlap said source region and drain region.

Claim 10

A method of manufacturing thin film transistors, comprising the steps of: a) forming a first thin silicon film on an insulation substrate; b) forming two patterns by selectively etching said first thin silicon film; c) adding impurities to said two patterns; d) disposing a second thin silicon film on said substrate, with at least a portion of said second thin silicon film being disposed between said two patterns and connecting said two patterns; e) forming, in turn, a gate insulation layer and an electrically conductive film on said two patterns and said second thin silicon film; f) forming a gate electrode by selectively etching said electrically conductive film; g) forming an insulation film on side walls of said gate electrode; and h) forming a source region and a drain region self-aligned to said gate electrode and said insulation film on said side walls by adding impurities to portions of said second thin silicon film with said gate electrode and said insulation film on side walls as a mask; wherein said gate electrode does not overlap said source and drain areas and is laterally offset from said source and drain areas.

Claim 11

A method of manufacturing thin film transistors, comprising the steps of: a) forming a first thin silicon film on an insulation substrate; b) forming two patterns by selectively etching said first thin silicon film; c) adding impurities to said two patterns; d) disposing a second thin silicon film on said substrate, with at least a portion of said second thin silicon film being disposed between said two patterns and connecting said two patterns; e) forming, in turn, a gate insulation layer and an electrically conductive film on said two patterns and said second thin silicon film; f) forming a gate electrode by selectively etching said electrically conductive film; g) forming an insulation film on side walls of said gate electrode; and h) forming a source region and a drain region self-aligned to said gate electrode and said insulation film on said side walls by adding impurities to portions of said second thin silicon film with said gate electrode and said insulation film on side walls as a mask; wherein said gate electrode does not overlap said source and drain areas and is laterally offset from said source and drain areas.

Claim 16

A method of manufacturing thin film transistors on an insulation substrate, comprising the steps of: a) forming a first thin silicon film on an insulation substrate; b) forming two patterns by selectively etching said first thin silicon c) disposing a second thin silicon film on said substrate, with at least a portion of said second thin silicon film being disposed between said two patterns and connecting said two patterns; d) forming, in turn, a gate insulating layer and an electrically conductive film on said two patterns and said second thin silicon film; e) forming a gate electrode by selectively etching said electrically conductive film; f) forming an insulation layer over said gate electrode, such that a portion of said insulation layer is formed on each side wall of said gate electrode; and g) forming a source region and a drain region self-aligned to said gate electrode and said portions of said insulation layer on the sidewalls by adding impurities to said two patterns and portions of said second thin silicon film with said gate electrode and said portions on the sidewalls as a mask; wherein said gate electrode does not overlap said source and drain areas and is laterally offset from said source and drain areas.

Claim 17

A method of manufacturing thin film transistors on an insulation substrate, comprising the steps of: a) forming a first thin silicon film on an insulation substrate; b) forming two patterns by selectively etching said first thin silicon c) disposing a second thin silicon film on said substrate, with at least a portion of said second thin silicon film being disposed between said two patterns and connecting said two patterns; d) forming, in turn, a gate insulating layer and an electrically conductive film on said two patterns and said second thin silicon film; e) forming a gate electrode by selectively etching said electrically conductive film; f) forming an insulation layer over said gate electrode, such that a portion of said insulation layer is formed on each side wall of said gate electrode; and g) forming a source region and a drain region self-aligned to said gate electrode and said portions of said insulation layer on the sidewalls by adding impurities to said two patterns and portions of said second thin silicon film with said gate electrode and said portions on the sidewalls as a mask; wherein said gate electrode does not overlap said source and drain areas and is laterally offset from said source and drain areas.